allwinner: Use the arisc to turn off ARM cores
PSCI requires a core to turn itself off, which we can't do properly by
just executing an algorithm on that very core. As a consequence we just
put a core into WFI on CPU_OFF right now.
To fix this let's task the "arisc" management processor (an OpenRISC
core) with that task of asserting reset and turning off the core's power
domain. We use a handcrafted sequence of OpenRISC instructions to
achieve this, and hand this data over to the new sunxi_execute_arisc_code()
routine.
The commented source code for this routine is provided in a separate file,
but the ATF code contains the already encoded instructions as data.
The H6 uses the same algorithm, but differs in the MMIO addresses, so
provide a SoC (family) specific copy of that code.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
diff --git a/plat/allwinner/common/sunxi_cpu_ops.c b/plat/allwinner/common/sunxi_cpu_ops.c
index 2db2697..3b732b5 100644
--- a/plat/allwinner/common/sunxi_cpu_ops.c
+++ b/plat/allwinner/common/sunxi_cpu_ops.c
@@ -4,11 +4,16 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
+#include <arch_helpers.h>
+#include <assert.h>
+#include <core_off_arisc.h>
#include <debug.h>
+#include <delay_timer.h>
#include <mmio.h>
+#include <platform.h>
#include <platform_def.h>
-#include <sunxi_mmap.h>
#include <sunxi_cpucfg.h>
+#include <sunxi_mmap.h>
#include <sunxi_private.h>
#include <utils_def.h>
@@ -39,16 +44,37 @@
void sunxi_cpu_off(unsigned int cluster, unsigned int core)
{
+ int corenr = cluster * PLATFORM_MAX_CPUS_PER_CLUSTER + core;
+
VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
/* Deassert DBGPWRDUP */
mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
- /* Activate the core output clamps */
- mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
- /* Assert CPU power-on reset */
- mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
- /* Remove power from the CPU */
- sunxi_cpu_disable_power(cluster, core);
+
+ /* We can't turn ourself off like this, but it works for other cores. */
+ if (plat_my_core_pos() != corenr) {
+ /* Activate the core output clamps, but not for core 0. */
+ if (corenr != 0)
+ mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
+ BIT(core));
+ /* Assert CPU power-on reset */
+ mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
+ /* Remove power from the CPU */
+ sunxi_cpu_disable_power(cluster, core);
+
+ return;
+ }
+
+ /* Simplifies assembly, all SoCs so far are single cluster anyway. */
+ assert(cluster == 0);
+
+ /*
+ * If we are supposed to turn ourself off, tell the arisc SCP
+ * to do that work for us. The code expects the core mask to be
+ * patched into the first instruction.
+ */
+ sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
+ 0, BIT_32(core));
}
void sunxi_cpu_on(unsigned int cluster, unsigned int core)