Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 1 | /* |
Harvey Hsieh | b9b374f | 2016-11-15 22:04:51 +0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | d292e5d | 2018-05-17 10:42:18 -0700 | [diff] [blame] | 3 | * Copyright (c) 2019-2020, NVIDIA Corporation. All rights reserved. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 4 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 5 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 6 | */ |
| 7 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 8 | #include <assert.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <string.h> |
| 10 | |
| 11 | #include <arch_helpers.h> |
| 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <lib/mmio.h> |
| 15 | #include <lib/utils.h> |
| 16 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 17 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 18 | #include <mce.h> |
| 19 | #include <memctrl.h> |
| 20 | #include <memctrl_v2.h> |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 21 | #include <smmu.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 22 | #include <tegra_def.h> |
Varun Wadekar | e81177d | 2016-07-18 17:43:41 -0700 | [diff] [blame] | 23 | #include <tegra_platform.h> |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 24 | #include <tegra_private.h> |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 25 | |
| 26 | /* Video Memory base and size (live values) */ |
| 27 | static uint64_t video_mem_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 28 | static uint64_t video_mem_size_mb; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 29 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 30 | /* |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 31 | * Init Memory controller during boot. |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 32 | */ |
| 33 | void tegra_memctrl_setup(void) |
| 34 | { |
| 35 | uint32_t val; |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 36 | const uint32_t *mc_streamid_override_regs; |
| 37 | uint32_t num_streamid_override_regs; |
| 38 | const mc_streamid_security_cfg_t *mc_streamid_sec_cfgs; |
| 39 | uint32_t num_streamid_sec_cfgs; |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 40 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 41 | uint32_t i; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 42 | |
| 43 | INFO("Tegra Memory Controller (v2)\n"); |
| 44 | |
| 45 | /* Program the SMMU pagesize */ |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 46 | tegra_smmu_init(); |
Varun Wadekar | cba0529 | 2017-11-29 17:14:24 -0800 | [diff] [blame] | 47 | |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 48 | /* Get the settings from the platform */ |
Anthony Zhou | 4408e88 | 2017-07-07 14:29:51 +0800 | [diff] [blame] | 49 | assert(plat_mc_settings != NULL); |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 50 | mc_streamid_override_regs = plat_mc_settings->streamid_override_cfg; |
| 51 | num_streamid_override_regs = plat_mc_settings->num_streamid_override_cfgs; |
| 52 | mc_streamid_sec_cfgs = plat_mc_settings->streamid_security_cfg; |
| 53 | num_streamid_sec_cfgs = plat_mc_settings->num_streamid_security_cfgs; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 54 | |
| 55 | /* Program all the Stream ID overrides */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 56 | for (i = 0; i < num_streamid_override_regs; i++) |
| 57 | tegra_mc_streamid_write_32(mc_streamid_override_regs[i], |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 58 | MC_STREAM_ID_MAX); |
| 59 | |
| 60 | /* Program the security config settings for all Stream IDs */ |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 61 | for (i = 0; i < num_streamid_sec_cfgs; i++) { |
| 62 | val = mc_streamid_sec_cfgs[i].override_enable << 16 | |
| 63 | mc_streamid_sec_cfgs[i].override_client_inputs << 8 | |
| 64 | mc_streamid_sec_cfgs[i].override_client_ns_flag << 0; |
| 65 | tegra_mc_streamid_write_32(mc_streamid_sec_cfgs[i].offset, val); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 66 | } |
| 67 | |
| 68 | /* |
| 69 | * All requests at boot time, and certain requests during |
| 70 | * normal run time, are physically addressed and must bypass |
| 71 | * the SMMU. The client hub logic implements a hardware bypass |
| 72 | * path around the Translation Buffer Units (TBU). During |
| 73 | * boot-time, the SMMU_BYPASS_CTRL register (which defaults to |
| 74 | * TBU_BYPASS mode) will be used to steer all requests around |
| 75 | * the uninitialized TBUs. During normal operation, this register |
| 76 | * is locked into TBU_BYPASS_SID config, which routes requests |
| 77 | * with special StreamID 0x7f on the bypass path and all others |
| 78 | * through the selected TBU. This is done to disable SMMU Bypass |
| 79 | * mode, as it could be used to circumvent SMMU security checks. |
| 80 | */ |
| 81 | tegra_mc_write_32(MC_SMMU_BYPASS_CONFIG, |
Pritesh Raithatha | 9eb5db5 | 2017-01-02 19:42:31 +0530 | [diff] [blame] | 82 | MC_SMMU_BYPASS_CONFIG_SETTINGS); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 83 | |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 84 | /* |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 85 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 86 | * Memory Controller traffic. This is needed as the Memory Controller |
| 87 | * boots with MSS having all control, but ROC provides a performance |
| 88 | * boost as compared to MSS. |
| 89 | */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 90 | if (plat_mc_settings->reconfig_mss_clients != NULL) { |
| 91 | plat_mc_settings->reconfig_mss_clients(); |
| 92 | } |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 93 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 94 | /* Program overrides for MC transactions */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 95 | if (plat_mc_settings->set_txn_overrides != NULL) { |
| 96 | plat_mc_settings->set_txn_overrides(); |
| 97 | } |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 98 | } |
Varun Wadekar | c9ac3e4 | 2016-02-17 15:07:49 -0800 | [diff] [blame] | 99 | |
Varun Wadekar | 87e44ff | 2016-03-03 13:22:39 -0800 | [diff] [blame] | 100 | /* |
| 101 | * Restore Memory Controller settings after "System Suspend" |
| 102 | */ |
| 103 | void tegra_memctrl_restore_settings(void) |
| 104 | { |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 105 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
| 106 | |
| 107 | assert(plat_mc_settings != NULL); |
| 108 | |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 109 | /* |
| 110 | * Re-configure MSS to allow ROC to deal with ordering of the |
| 111 | * Memory Controller traffic. This is needed as the Memory Controller |
| 112 | * resets during System Suspend with MSS having all control, but ROC |
| 113 | * provides a performance boost as compared to MSS. |
| 114 | */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 115 | if (plat_mc_settings->reconfig_mss_clients != NULL) { |
| 116 | plat_mc_settings->reconfig_mss_clients(); |
| 117 | } |
Varun Wadekar | a0f2697 | 2016-03-11 17:18:51 -0800 | [diff] [blame] | 118 | |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 119 | /* Program overrides for MC transactions */ |
Puneet Saxena | cf8c0e2 | 2017-08-04 17:19:55 +0530 | [diff] [blame] | 120 | if (plat_mc_settings->set_txn_overrides != NULL) { |
| 121 | plat_mc_settings->set_txn_overrides(); |
| 122 | } |
Varun Wadekar | ad45ef7 | 2017-04-03 13:44:57 -0700 | [diff] [blame] | 123 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 124 | /* video memory carveout region */ |
Anthony Zhou | 0e07e45 | 2017-07-26 17:16:54 +0800 | [diff] [blame] | 125 | if (video_mem_base != 0ULL) { |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 126 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, |
| 127 | (uint32_t)video_mem_base); |
| 128 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 129 | (uint32_t)(video_mem_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 130 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, video_mem_size_mb); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 131 | |
| 132 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 133 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 134 | * CCPLEX. |
| 135 | */ |
| 136 | mce_update_gsc_videomem(); |
| 137 | } |
| 138 | } |
| 139 | |
| 140 | /* |
| 141 | * Secure the BL31 DRAM aperture. |
| 142 | * |
| 143 | * phys_base = physical base of TZDRAM aperture |
| 144 | * size_in_bytes = size of aperture in bytes |
| 145 | */ |
| 146 | void tegra_memctrl_tzdram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 147 | { |
| 148 | /* |
Varun Wadekar | f3cd509 | 2017-10-30 14:35:17 -0700 | [diff] [blame] | 149 | * Perform platform specific steps. |
Harvey Hsieh | c95802d | 2016-07-29 20:10:59 +0800 | [diff] [blame] | 150 | */ |
Varun Wadekar | f3cd509 | 2017-10-30 14:35:17 -0700 | [diff] [blame] | 151 | plat_memctrl_tzdram_setup(phys_base, size_in_bytes); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 152 | } |
| 153 | |
| 154 | /* |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 155 | * Secure the BL31 TZRAM aperture. |
| 156 | * |
| 157 | * phys_base = physical base of TZRAM aperture |
| 158 | * size_in_bytes = size of aperture in bytes |
| 159 | */ |
| 160 | void tegra_memctrl_tzram_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 161 | { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 162 | uint32_t index; |
| 163 | uint32_t total_128kb_blocks = size_in_bytes >> 17; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 164 | uint32_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 165 | uint32_t val; |
| 166 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 167 | INFO("Configuring TrustZone SRAM Memory Carveout\n"); |
| 168 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 169 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 170 | * Reset the access configuration registers to restrict access |
| 171 | * to the TZRAM aperture |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 172 | */ |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 173 | for (index = MC_TZRAM_CLIENT_ACCESS0_CFG0; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 174 | index < ((uint32_t)MC_TZRAM_CARVEOUT_CFG + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 175 | index += 4U) { |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 176 | tegra_mc_write_32(index, 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 177 | } |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 178 | |
| 179 | /* |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 180 | * Enable CPU access configuration registers to access the TZRAM aperture |
| 181 | */ |
| 182 | if (!tegra_chipid_is_t186()) { |
| 183 | val = tegra_mc_read_32(MC_TZRAM_CLIENT_ACCESS1_CFG0); |
| 184 | val |= TZRAM_ALLOW_MPCORER | TZRAM_ALLOW_MPCOREW; |
| 185 | tegra_mc_write_32(MC_TZRAM_CLIENT_ACCESS1_CFG0, val); |
| 186 | } |
| 187 | |
| 188 | /* |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 189 | * Set the TZRAM base. TZRAM base must be 4k aligned, at least. |
| 190 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 191 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 192 | tegra_mc_write_32(MC_TZRAM_BASE_LO, (uint32_t)phys_base); |
| 193 | tegra_mc_write_32(MC_TZRAM_BASE_HI, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 194 | (uint32_t)(phys_base >> 32) & MC_GSC_BASE_HI_MASK); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 195 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 196 | /* |
| 197 | * Set the TZRAM size |
| 198 | * |
| 199 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 200 | * blocks) |
| 201 | * |
| 202 | */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 203 | val = (residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 204 | total_128kb_blocks; |
| 205 | tegra_mc_write_32(MC_TZRAM_SIZE, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 206 | |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 207 | /* |
| 208 | * Lock the configuration settings by disabling TZ-only lock |
| 209 | * and locking the configuration against any future changes |
| 210 | * at all. |
| 211 | */ |
| 212 | val = tegra_mc_read_32(MC_TZRAM_CARVEOUT_CFG); |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 213 | val &= (uint32_t)~MC_GSC_ENABLE_TZ_LOCK_BIT; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 214 | val |= MC_GSC_LOCK_CFG_SETTINGS_BIT; |
Steven Kao | b688d38 | 2017-09-06 13:32:21 +0800 | [diff] [blame] | 215 | if (!tegra_chipid_is_t186()) { |
| 216 | val |= MC_GSC_ENABLE_CPU_SECURE_BIT; |
| 217 | } |
Varun Wadekar | e6d4322 | 2016-05-25 16:35:04 -0700 | [diff] [blame] | 218 | tegra_mc_write_32(MC_TZRAM_CARVEOUT_CFG, val); |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 219 | |
| 220 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 221 | * MCE propagates the security configuration values across the |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 222 | * CCPLEX. |
| 223 | */ |
| 224 | mce_update_gsc_tzram(); |
| 225 | } |
| 226 | |
Pritesh Raithatha | 75c9443 | 2018-08-03 15:48:15 +0530 | [diff] [blame] | 227 | /* |
| 228 | * Save MC settings before "System Suspend" to TZDRAM |
| 229 | */ |
| 230 | void tegra_mc_save_context(uint64_t mc_ctx_addr) |
| 231 | { |
| 232 | const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings(); |
| 233 | uint32_t i, num_entries = 0; |
| 234 | mc_regs_t *mc_ctx_regs; |
| 235 | const plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params(); |
| 236 | uint64_t tzdram_base = params_from_bl2->tzdram_base; |
| 237 | uint64_t tzdram_end = tzdram_base + params_from_bl2->tzdram_size; |
| 238 | |
| 239 | assert((mc_ctx_addr >= tzdram_base) && (mc_ctx_addr <= tzdram_end)); |
| 240 | |
| 241 | /* get MC context table */ |
| 242 | mc_ctx_regs = plat_mc_settings->get_mc_system_suspend_ctx(); |
| 243 | assert(mc_ctx_regs != NULL); |
| 244 | |
| 245 | /* |
| 246 | * mc_ctx_regs[0].val contains the size of the context table minus |
| 247 | * the last entry. Sanity check the table size before we start with |
| 248 | * the context save operation. |
| 249 | */ |
| 250 | while (mc_ctx_regs[num_entries].reg != 0xFFFFFFFFU) { |
| 251 | num_entries++; |
| 252 | } |
| 253 | |
| 254 | /* panic if the sizes do not match */ |
| 255 | if (num_entries != mc_ctx_regs[0].val) { |
| 256 | ERROR("MC context size mismatch!"); |
| 257 | panic(); |
| 258 | } |
| 259 | |
| 260 | /* save MC register values */ |
| 261 | for (i = 1U; i < num_entries; i++) { |
| 262 | mc_ctx_regs[i].val = mmio_read_32(mc_ctx_regs[i].reg); |
| 263 | } |
| 264 | |
| 265 | /* increment by 1 to take care of the last entry */ |
| 266 | num_entries++; |
| 267 | |
| 268 | /* Save MC config settings */ |
| 269 | (void)memcpy((void *)mc_ctx_addr, mc_ctx_regs, |
| 270 | sizeof(mc_regs_t) * num_entries); |
| 271 | |
| 272 | /* save the MC table address */ |
| 273 | mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_LO, |
| 274 | (uint32_t)mc_ctx_addr); |
| 275 | mmio_write_32(TEGRA_SCRATCH_BASE + SCRATCH_MC_TABLE_ADDR_HI, |
| 276 | (uint32_t)(mc_ctx_addr >> 32)); |
| 277 | } |
| 278 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 279 | static void tegra_lock_videomem_nonoverlap(uint64_t phys_base, |
| 280 | uint64_t size_in_bytes) |
| 281 | { |
| 282 | uint32_t index; |
| 283 | uint64_t total_128kb_blocks = size_in_bytes >> 17; |
| 284 | uint64_t residual_4kb_blocks = (size_in_bytes & (uint32_t)0x1FFFF) >> 12; |
| 285 | uint64_t val; |
| 286 | |
| 287 | /* |
| 288 | * Reset the access configuration registers to restrict access to |
| 289 | * old Videomem aperture |
| 290 | */ |
| 291 | for (index = MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0; |
| 292 | index < ((uint32_t)MC_VIDEO_PROTECT_CLEAR_ACCESS_CFG0 + (uint32_t)MC_GSC_CONFIG_REGS_SIZE); |
| 293 | index += 4U) { |
| 294 | tegra_mc_write_32(index, 0); |
| 295 | } |
| 296 | |
| 297 | /* |
| 298 | * Set the base. It must be 4k aligned, at least. |
| 299 | */ |
| 300 | assert((phys_base & (uint64_t)0xFFF) == 0U); |
| 301 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, (uint32_t)phys_base); |
| 302 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, |
| 303 | (uint32_t)(phys_base >> 32) & (uint32_t)MC_GSC_BASE_HI_MASK); |
| 304 | |
| 305 | /* |
| 306 | * Set the aperture size |
| 307 | * |
| 308 | * total size = (number of 128KB blocks) + (number of remaining 4KB |
| 309 | * blocks) |
| 310 | * |
| 311 | */ |
| 312 | val = (uint32_t)((residual_4kb_blocks << MC_GSC_SIZE_RANGE_4KB_SHIFT) | |
| 313 | total_128kb_blocks); |
| 314 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, (uint32_t)val); |
| 315 | |
| 316 | /* |
| 317 | * Lock the configuration settings by enabling TZ-only lock and |
| 318 | * locking the configuration against any future changes from NS |
| 319 | * world. |
| 320 | */ |
| 321 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_CFG, |
| 322 | (uint32_t)MC_GSC_ENABLE_TZ_LOCK_BIT); |
| 323 | |
| 324 | /* |
| 325 | * MCE propagates the GSC configuration values across the |
| 326 | * CCPLEX. |
| 327 | */ |
| 328 | } |
| 329 | |
| 330 | static void tegra_unlock_videomem_nonoverlap(void) |
| 331 | { |
| 332 | /* Clear the base */ |
| 333 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_LO, 0); |
| 334 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_BASE_HI, 0); |
| 335 | |
| 336 | /* Clear the size */ |
| 337 | tegra_mc_write_32(MC_VIDEO_PROTECT_CLEAR_SIZE, 0); |
| 338 | } |
| 339 | |
| 340 | static void tegra_clear_videomem(uintptr_t non_overlap_area_start, |
| 341 | unsigned long long non_overlap_area_size) |
| 342 | { |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 343 | int ret; |
| 344 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 345 | /* |
| 346 | * Map the NS memory first, clean it and then unmap it. |
| 347 | */ |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 348 | ret = mmap_add_dynamic_region(non_overlap_area_start, /* PA */ |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 349 | non_overlap_area_start, /* VA */ |
| 350 | non_overlap_area_size, /* size */ |
| 351 | MT_NS | MT_RW | MT_EXECUTE_NEVER); /* attrs */ |
Varun Wadekar | 117a2e0 | 2017-08-03 11:40:34 -0700 | [diff] [blame] | 352 | assert(ret == 0); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 353 | |
| 354 | zero_normalmem((void *)non_overlap_area_start, non_overlap_area_size); |
| 355 | flush_dcache_range(non_overlap_area_start, non_overlap_area_size); |
| 356 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 357 | (void)mmap_remove_dynamic_region(non_overlap_area_start, |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 358 | non_overlap_area_size); |
| 359 | } |
| 360 | |
Varun Wadekar | 13e7dc4 | 2015-12-30 15:15:08 -0800 | [diff] [blame] | 361 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 362 | * Program the Video Memory carveout region |
| 363 | * |
| 364 | * phys_base = physical base of aperture |
| 365 | * size_in_bytes = size of aperture in bytes |
| 366 | */ |
| 367 | void tegra_memctrl_videomem_setup(uint64_t phys_base, uint32_t size_in_bytes) |
| 368 | { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 369 | uintptr_t vmem_end_old = video_mem_base + (video_mem_size_mb << 20); |
| 370 | uintptr_t vmem_end_new = phys_base + size_in_bytes; |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 371 | unsigned long long non_overlap_area_size; |
Varun Wadekar | e60f1bf | 2016-02-17 10:10:50 -0800 | [diff] [blame] | 372 | |
| 373 | /* |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 374 | * Setup the Memory controller to restrict CPU accesses to the Video |
| 375 | * Memory region |
| 376 | */ |
| 377 | INFO("Configuring Video Memory Carveout\n"); |
| 378 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 379 | /* |
| 380 | * Configure Memory Controller directly for the first time. |
| 381 | */ |
| 382 | if (video_mem_base == 0U) |
| 383 | goto done; |
| 384 | |
| 385 | /* |
| 386 | * Lock the non overlapping memory being cleared so that other masters |
| 387 | * do not accidently write to it. The memory would be unlocked once |
| 388 | * the non overlapping region is cleared and the new memory |
| 389 | * settings take effect. |
| 390 | */ |
| 391 | tegra_lock_videomem_nonoverlap(video_mem_base, |
| 392 | video_mem_size_mb << 20); |
| 393 | |
| 394 | /* |
| 395 | * Clear the old regions now being exposed. The following cases |
| 396 | * can occur - |
| 397 | * |
| 398 | * 1. clear whole old region (no overlap with new region) |
| 399 | * 2. clear old sub-region below new base |
| 400 | * 3. clear old sub-region above new end |
| 401 | */ |
| 402 | INFO("Cleaning previous Video Memory Carveout\n"); |
| 403 | |
Anthony Zhou | 0844b97 | 2017-06-28 16:35:54 +0800 | [diff] [blame] | 404 | if ((phys_base > vmem_end_old) || (video_mem_base > vmem_end_new)) { |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 405 | tegra_clear_videomem(video_mem_base, |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 406 | video_mem_size_mb << 20U); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 407 | } else { |
| 408 | if (video_mem_base < phys_base) { |
| 409 | non_overlap_area_size = phys_base - video_mem_base; |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 410 | tegra_clear_videomem(video_mem_base, non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 411 | } |
| 412 | if (vmem_end_old > vmem_end_new) { |
| 413 | non_overlap_area_size = vmem_end_old - vmem_end_new; |
Varun Wadekar | 8b1c004 | 2019-09-05 08:17:02 -0700 | [diff] [blame] | 414 | tegra_clear_videomem(vmem_end_new, non_overlap_area_size); |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 415 | } |
| 416 | } |
| 417 | |
| 418 | done: |
| 419 | /* program the Videomem aperture */ |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 420 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO, (uint32_t)phys_base); |
| 421 | tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI, |
| 422 | (uint32_t)(phys_base >> 32)); |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 423 | tegra_mc_write_32(MC_VIDEO_PROTECT_SIZE_MB, size_in_bytes >> 20); |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 424 | |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 425 | /* unlock the previous locked nonoverlapping aperture */ |
| 426 | tegra_unlock_videomem_nonoverlap(); |
| 427 | |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 428 | /* store new values */ |
| 429 | video_mem_base = phys_base; |
Varun Wadekar | 7058aee | 2016-04-25 09:01:46 -0700 | [diff] [blame] | 430 | video_mem_size_mb = size_in_bytes >> 20; |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 431 | |
| 432 | /* |
Varun Wadekar | 153982c | 2016-12-21 14:50:18 -0800 | [diff] [blame] | 433 | * MCE propagates the VideoMem configuration values across the |
Varun Wadekar | cd5a2f5 | 2015-09-20 15:08:22 +0530 | [diff] [blame] | 434 | * CCPLEX. |
| 435 | */ |
| 436 | mce_update_gsc_videomem(); |
| 437 | } |
Varun Wadekar | c92050b | 2017-03-29 14:57:29 -0700 | [diff] [blame] | 438 | |
| 439 | /* |
| 440 | * This feature exists only for v1 of the Tegra Memory Controller. |
| 441 | */ |
| 442 | void tegra_memctrl_disable_ahb_redirection(void) |
| 443 | { |
| 444 | ; /* do nothing */ |
| 445 | } |
Harvey Hsieh | 359be95 | 2017-08-21 15:01:53 +0800 | [diff] [blame] | 446 | |
| 447 | void tegra_memctrl_clear_pending_interrupts(void) |
| 448 | { |
| 449 | ; /* do nothing */ |
| 450 | } |