| Yatharth Kochar | dafb247 | 2016-06-30 14:52:12 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <asm_macros.S> |
| 33 | #include <bl_common.h> |
| 34 | |
| 35 | |
| 36 | .globl bl2_vector_table |
| 37 | .globl bl2_entrypoint |
| 38 | |
| 39 | |
| 40 | vector_base bl2_vector_table |
| 41 | b bl2_entrypoint |
| 42 | b report_exception /* Undef */ |
| 43 | b report_exception /* SVC call */ |
| 44 | b report_exception /* Prefetch abort */ |
| 45 | b report_exception /* Data abort */ |
| 46 | b report_exception /* Reserved */ |
| 47 | b report_exception /* IRQ */ |
| 48 | b report_exception /* FIQ */ |
| 49 | |
| 50 | |
| 51 | func bl2_entrypoint |
| 52 | /*--------------------------------------------- |
| 53 | * Save from r1 the extents of the trusted ram |
| 54 | * available to BL2 for future use. |
| 55 | * r0 is not currently used. |
| 56 | * --------------------------------------------- |
| 57 | */ |
| 58 | mov r11, r1 |
| 59 | |
| 60 | /* --------------------------------------------- |
| 61 | * Set the exception vector to something sane. |
| 62 | * --------------------------------------------- |
| 63 | */ |
| 64 | ldr r0, =bl2_vector_table |
| 65 | stcopr r0, VBAR |
| 66 | isb |
| 67 | |
| 68 | /* ----------------------------------------------------- |
| 69 | * Enable the instruction cache |
| 70 | * ----------------------------------------------------- |
| 71 | */ |
| 72 | ldcopr r0, SCTLR |
| 73 | orr r0, r0, #SCTLR_I_BIT |
| 74 | stcopr r0, SCTLR |
| 75 | isb |
| 76 | |
| 77 | /* --------------------------------------------- |
| 78 | * Since BL2 executes after BL1, it is assumed |
| 79 | * here that BL1 has already has done the |
| 80 | * necessary register initializations. |
| 81 | * --------------------------------------------- |
| 82 | */ |
| 83 | |
| 84 | /* --------------------------------------------- |
| 85 | * Invalidate the RW memory used by the BL2 |
| 86 | * image. This includes the data and NOBITS |
| 87 | * sections. This is done to safeguard against |
| 88 | * possible corruption of this memory by dirty |
| 89 | * cache lines in a system cache as a result of |
| 90 | * use by an earlier boot loader stage. |
| 91 | * --------------------------------------------- |
| 92 | */ |
| 93 | ldr r0, =__RW_START__ |
| 94 | ldr r1, =__RW_END__ |
| 95 | sub r1, r1, r0 |
| 96 | bl inv_dcache_range |
| 97 | |
| 98 | /* --------------------------------------------- |
| 99 | * Zero out NOBITS sections. There are 2 of them: |
| 100 | * - the .bss section; |
| 101 | * - the coherent memory section. |
| 102 | * --------------------------------------------- |
| 103 | */ |
| 104 | ldr r0, =__BSS_START__ |
| 105 | ldr r1, =__BSS_SIZE__ |
| 106 | bl zeromem |
| 107 | |
| 108 | #if USE_COHERENT_MEM |
| 109 | ldr r0, =__COHERENT_RAM_START__ |
| 110 | ldr r1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
| 111 | bl zeromem |
| 112 | #endif |
| 113 | |
| 114 | /* -------------------------------------------- |
| 115 | * Allocate a stack whose memory will be marked |
| 116 | * as Normal-IS-WBWA when the MMU is enabled. |
| 117 | * There is no risk of reading stale stack |
| 118 | * memory after enabling the MMU as only the |
| 119 | * primary cpu is running at the moment. |
| 120 | * -------------------------------------------- |
| 121 | */ |
| 122 | bl plat_set_my_stack |
| 123 | |
| 124 | /* --------------------------------------------- |
| 125 | * Perform early platform setup & platform |
| 126 | * specific early arch. setup e.g. mmu setup |
| 127 | * --------------------------------------------- |
| 128 | */ |
| 129 | mov r0, r11 |
| 130 | bl bl2_early_platform_setup |
| 131 | bl bl2_plat_arch_setup |
| 132 | |
| 133 | /* --------------------------------------------- |
| 134 | * Jump to main function. |
| 135 | * --------------------------------------------- |
| 136 | */ |
| 137 | bl bl2_main |
| 138 | |
| 139 | /* --------------------------------------------- |
| 140 | * Should never reach this point. |
| 141 | * --------------------------------------------- |
| 142 | */ |
| Jeenu Viswambharan | 68aef10 | 2016-11-30 15:21:11 +0000 | [diff] [blame] | 143 | no_ret plat_panic_handler |
| Yatharth Kochar | dafb247 | 2016-06-30 14:52:12 +0100 | [diff] [blame] | 144 | |
| 145 | endfunc bl2_entrypoint |