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Yann Gautier66386952018-07-05 16:49:51 +02001// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
2/*
Yann Gautier3edc7c32019-05-20 19:17:08 +02003 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
Yann Gautier66386952018-07-05 16:49:51 +02004 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
5 */
Yann Gautier7b7e4bf2019-01-17 19:16:03 +01006#include <dt-bindings/interrupt-controller/arm-gic.h>
Yann Gautier66386952018-07-05 16:49:51 +02007#include <dt-bindings/clock/stm32mp1-clks.h>
8#include <dt-bindings/reset/stm32mp1-resets.h>
9
10/ {
11 #address-cells = <1>;
12 #size-cells = <1>;
13
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010014 intc: interrupt-controller@a0021000 {
15 compatible = "arm,cortex-a7-gic";
16 #interrupt-cells = <3>;
17 interrupt-controller;
18 reg = <0xa0021000 0x1000>,
19 <0xa0022000 0x2000>;
Yann Gautier66386952018-07-05 16:49:51 +020020 };
21
22 clocks {
23 clk_hse: clk-hse {
24 #clock-cells = <0>;
25 compatible = "fixed-clock";
26 clock-frequency = <24000000>;
27 };
28
29 clk_hsi: clk-hsi {
30 #clock-cells = <0>;
31 compatible = "fixed-clock";
32 clock-frequency = <64000000>;
33 };
34
35 clk_lse: clk-lse {
36 #clock-cells = <0>;
37 compatible = "fixed-clock";
38 clock-frequency = <32768>;
39 };
40
41 clk_lsi: clk-lsi {
42 #clock-cells = <0>;
43 compatible = "fixed-clock";
44 clock-frequency = <32000>;
45 };
46
47 clk_csi: clk-csi {
48 #clock-cells = <0>;
49 compatible = "fixed-clock";
50 clock-frequency = <4000000>;
51 };
52
53 clk_i2s_ckin: i2s_ckin {
54 #clock-cells = <0>;
55 compatible = "fixed-clock";
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010056 clock-frequency = <0>;
Yann Gautier66386952018-07-05 16:49:51 +020057 };
58
59 clk_dsi_phy: ck_dsi_phy {
60 #clock-cells = <0>;
61 compatible = "fixed-clock";
62 clock-frequency = <0>;
63 };
Yann Gautier66386952018-07-05 16:49:51 +020064 };
65
66 soc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010070 interrupt-parent = <&intc>;
Yann Gautier66386952018-07-05 16:49:51 +020071 ranges;
72
Yann Gautier990ecea2019-06-04 17:24:36 +020073 timers12: timer@40006000 {
74 #address-cells = <1>;
75 #size-cells = <0>;
76 compatible = "st,stm32-timers";
77 reg = <0x40006000 0x400>;
78 clocks = <&rcc TIM12_K>;
79 clock-names = "int";
80 status = "disabled";
81 };
82
Yann Gautier66386952018-07-05 16:49:51 +020083 usart2: serial@4000e000 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010084 compatible = "st,stm32h7-uart";
Yann Gautier66386952018-07-05 16:49:51 +020085 reg = <0x4000e000 0x400>;
86 clocks = <&rcc USART2_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010087 resets = <&rcc USART2_R>;
Yann Gautier66386952018-07-05 16:49:51 +020088 status = "disabled";
89 };
90
91 usart3: serial@4000f000 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010092 compatible = "st,stm32h7-uart";
Yann Gautier66386952018-07-05 16:49:51 +020093 reg = <0x4000f000 0x400>;
94 clocks = <&rcc USART3_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +010095 resets = <&rcc USART3_R>;
Yann Gautier66386952018-07-05 16:49:51 +020096 status = "disabled";
97 };
98
99 uart4: serial@40010000 {
100 compatible = "st,stm32h7-uart";
101 reg = <0x40010000 0x400>;
102 clocks = <&rcc UART4_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100103 resets = <&rcc UART4_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200104 status = "disabled";
105 };
106
107 uart5: serial@40011000 {
108 compatible = "st,stm32h7-uart";
109 reg = <0x40011000 0x400>;
110 clocks = <&rcc UART5_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100111 resets = <&rcc UART5_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200112 status = "disabled";
113 };
114
115
116 uart7: serial@40018000 {
117 compatible = "st,stm32h7-uart";
118 reg = <0x40018000 0x400>;
119 clocks = <&rcc UART7_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100120 resets = <&rcc UART7_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200121 status = "disabled";
122 };
123
124 uart8: serial@40019000 {
125 compatible = "st,stm32h7-uart";
126 reg = <0x40019000 0x400>;
127 clocks = <&rcc UART8_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100128 resets = <&rcc UART8_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200129 status = "disabled";
130 };
131
132 usart6: serial@44003000 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100133 compatible = "st,stm32h7-uart";
Yann Gautier66386952018-07-05 16:49:51 +0200134 reg = <0x44003000 0x400>;
135 clocks = <&rcc USART6_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100136 resets = <&rcc USART6_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200137 status = "disabled";
138 };
139
Yann Gautier990ecea2019-06-04 17:24:36 +0200140 timers15: timer@44006000 {
141 #address-cells = <1>;
142 #size-cells = <0>;
143 compatible = "st,stm32-timers";
144 reg = <0x44006000 0x400>;
145 clocks = <&rcc TIM15_K>;
146 clock-names = "int";
147 status = "disabled";
148 };
149
Yann Gautier66386952018-07-05 16:49:51 +0200150 sdmmc3: sdmmc@48004000 {
Yann Gautier990ecea2019-06-04 17:24:36 +0200151 compatible = "arm,pl18x", "arm,primecell";
152 arm,primecell-periphid = <0x00253180>;
Yann Gautier66386952018-07-05 16:49:51 +0200153 reg = <0x48004000 0x400>, <0x48005000 0x400>;
Yann Gautier66386952018-07-05 16:49:51 +0200154 clocks = <&rcc SDMMC3_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100155 clock-names = "apb_pclk";
Yann Gautier66386952018-07-05 16:49:51 +0200156 resets = <&rcc SDMMC3_R>;
157 cap-sd-highspeed;
158 cap-mmc-highspeed;
159 max-frequency = <120000000>;
160 status = "disabled";
161 };
162
Yann Gautier990ecea2019-06-04 17:24:36 +0200163 usbotg_hs: usb-otg@49000000 {
164 compatible = "st,stm32mp1-hsotg", "snps,dwc2";
165 reg = <0x49000000 0x10000>;
166 clocks = <&rcc USBO_K>;
167 clock-names = "otg";
168 resets = <&rcc USBO_R>;
169 reset-names = "dwc2";
170 status = "disabled";
171 };
172
Yann Gautier66386952018-07-05 16:49:51 +0200173 rcc: rcc@50000000 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100174 compatible = "st,stm32mp1-rcc", "syscon";
175 reg = <0x50000000 0x1000>;
Yann Gautier66386952018-07-05 16:49:51 +0200176 #clock-cells = <1>;
177 #reset-cells = <1>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100178 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
Yann Gautier66386952018-07-05 16:49:51 +0200179 };
180
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100181 pwr: pwr@50001000 {
182 compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd";
183 reg = <0x50001000 0x400>;
Yann Gautier66386952018-07-05 16:49:51 +0200184 };
185
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100186 exti: interrupt-controller@5000d000 {
187 compatible = "st,stm32mp1-exti", "syscon";
188 interrupt-controller;
189 #interrupt-cells = <2>;
190 reg = <0x5000d000 0x400>;
191
192 /* exti_pwr is an extra interrupt controller used for
193 * EXTI 55 to 60. It's mapped on pwr interrupt
194 * controller.
195 */
196 exti_pwr: exti-pwr {
197 interrupt-controller;
198 #interrupt-cells = <2>;
199 interrupt-parent = <&pwr>;
200 st,irq-number = <6>;
201 };
202 };
203
Yann Gautier3edc7c32019-05-20 19:17:08 +0200204 syscfg: syscon@50020000 {
205 compatible = "st,stm32mp157-syscfg", "syscon";
206 reg = <0x50020000 0x400>;
207 clocks = <&rcc SYSCFG>;
208 };
209
Yann Gautier990ecea2019-06-04 17:24:36 +0200210 cryp1: cryp@54001000 {
211 compatible = "st,stm32mp1-cryp";
212 reg = <0x54001000 0x400>;
213 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
214 clocks = <&rcc CRYP1>;
215 resets = <&rcc CRYP1_R>;
216 status = "disabled";
217 };
218
219 hash1: hash@54002000 {
220 compatible = "st,stm32f756-hash";
221 reg = <0x54002000 0x400>;
222 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
223 clocks = <&rcc HASH1>;
224 resets = <&rcc HASH1_R>;
225 status = "disabled";
226 };
227
Yann Gautier66386952018-07-05 16:49:51 +0200228 rng1: rng@54003000 {
229 compatible = "st,stm32-rng";
230 reg = <0x54003000 0x400>;
231 clocks = <&rcc RNG1_K>;
232 resets = <&rcc RNG1_R>;
233 status = "disabled";
234 };
235
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100236 fmc: nand-controller@58002000 {
237 compatible = "st,stm32mp15-fmc2";
Yann Gautier66386952018-07-05 16:49:51 +0200238 reg = <0x58002000 0x1000>,
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100239 <0x80000000 0x1000>,
240 <0x88010000 0x1000>,
241 <0x88020000 0x1000>,
242 <0x81000000 0x1000>,
243 <0x89010000 0x1000>,
244 <0x89020000 0x1000>;
Yann Gautier66386952018-07-05 16:49:51 +0200245 clocks = <&rcc FMC_K>;
246 resets = <&rcc FMC_R>;
247 status = "disabled";
248 };
249
250 qspi: qspi@58003000 {
251 compatible = "st,stm32f469-qspi";
252 reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100253 reg-names = "qspi", "qspi_mm";
Yann Gautier66386952018-07-05 16:49:51 +0200254 clocks = <&rcc QSPI_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100255 resets = <&rcc QSPI_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200256 status = "disabled";
257 };
258
259 sdmmc1: sdmmc@58005000 {
Yann Gautier990ecea2019-06-04 17:24:36 +0200260 compatible = "arm,pl18x", "arm,primecell";
261 arm,primecell-periphid = <0x00253180>;
Yann Gautier66386952018-07-05 16:49:51 +0200262 reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
Yann Gautier66386952018-07-05 16:49:51 +0200263 clocks = <&rcc SDMMC1_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100264 clock-names = "apb_pclk";
Yann Gautier66386952018-07-05 16:49:51 +0200265 resets = <&rcc SDMMC1_R>;
266 cap-sd-highspeed;
267 cap-mmc-highspeed;
268 max-frequency = <120000000>;
269 status = "disabled";
270 };
271
272 sdmmc2: sdmmc@58007000 {
Yann Gautier990ecea2019-06-04 17:24:36 +0200273 compatible = "arm,pl18x", "arm,primecell";
274 arm,primecell-periphid = <0x00253180>;
Yann Gautier66386952018-07-05 16:49:51 +0200275 reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
Yann Gautier66386952018-07-05 16:49:51 +0200276 clocks = <&rcc SDMMC2_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100277 clock-names = "apb_pclk";
Yann Gautier66386952018-07-05 16:49:51 +0200278 resets = <&rcc SDMMC2_R>;
279 cap-sd-highspeed;
280 cap-mmc-highspeed;
281 max-frequency = <120000000>;
282 status = "disabled";
283 };
284
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100285 iwdg2: watchdog@5a002000 {
Yann Gautier66386952018-07-05 16:49:51 +0200286 compatible = "st,stm32mp1-iwdg";
287 reg = <0x5a002000 0x400>;
288 clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
289 clock-names = "pclk", "lsi";
290 status = "disabled";
291 };
292
293 usart1: serial@5c000000 {
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100294 compatible = "st,stm32h7-uart";
Yann Gautier66386952018-07-05 16:49:51 +0200295 reg = <0x5c000000 0x400>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100296 interrupt-names = "event", "wakeup";
297 interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
298 <&exti 26 1>;
Yann Gautier66386952018-07-05 16:49:51 +0200299 clocks = <&rcc USART1_K>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100300 resets = <&rcc USART1_R>;
Yann Gautier66386952018-07-05 16:49:51 +0200301 status = "disabled";
302 };
303
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100304 spi6: spi@5c001000 {
305 #address-cells = <1>;
306 #size-cells = <0>;
307 compatible = "st,stm32h7-spi";
308 reg = <0x5c001000 0x400>;
309 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
310 clocks = <&rcc SPI6_K>;
311 resets = <&rcc SPI6_R>;
312 status = "disabled";
313 };
314
Yann Gautier66386952018-07-05 16:49:51 +0200315 i2c4: i2c@5c002000 {
316 compatible = "st,stm32f7-i2c";
317 reg = <0x5c002000 0x400>;
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100318 interrupt-names = "event", "error", "wakeup";
319 interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
320 <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
321 <&exti 24 1>;
Yann Gautier66386952018-07-05 16:49:51 +0200322 clocks = <&rcc I2C4_K>;
323 resets = <&rcc I2C4_R>;
324 #address-cells = <1>;
325 #size-cells = <0>;
326 status = "disabled";
327 };
328
329 rtc: rtc@5c004000 {
330 compatible = "st,stm32mp1-rtc";
331 reg = <0x5c004000 0x400>;
332 clocks = <&rcc RTCAPB>, <&rcc RTC>;
333 clock-names = "pclk", "rtc_ck";
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100334 interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
335 <&exti 19 1>;
336 status = "disabled";
337 };
338
339 bsec: nvmem@5c005000 {
340 compatible = "st,stm32mp15-bsec";
341 reg = <0x5c005000 0x400>;
342 #address-cells = <1>;
343 #size-cells = <1>;
344 ts_cal1: calib@5c {
345 reg = <0x5c 0x2>;
346 };
347 ts_cal2: calib@5e {
348 reg = <0x5e 0x2>;
349 };
350 };
351
Etienne Carriere41e739d2020-06-03 18:12:20 +0200352 etzpc: etzpc@5c007000 {
353 compatible = "st,stm32-etzpc";
354 reg = <0x5C007000 0x400>;
355 clocks = <&rcc TZPC>;
356 status = "disabled";
357 secure-status = "okay";
358 };
359
Yann Gautier7b7e4bf2019-01-17 19:16:03 +0100360 i2c6: i2c@5c009000 {
361 compatible = "st,stm32f7-i2c";
362 reg = <0x5c009000 0x400>;
363 interrupt-names = "event", "error", "wakeup";
364 interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
365 <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
366 <&exti 54 1>;
367 clocks = <&rcc I2C6_K>;
368 resets = <&rcc I2C6_R>;
369 #address-cells = <1>;
370 #size-cells = <0>;
371 status = "disabled";
Yann Gautier66386952018-07-05 16:49:51 +0200372 };
Yann Gautier66386952018-07-05 16:49:51 +0200373 };
374};