fdts/stm32mp157c.dtsi

// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause)
/*
 * Copyright (C) STMicroelectronics 2017-2019 - All Rights Reserved
 * Author: Ludovic Barre <ludovic.barre@st.com> for STMicroelectronics.
 */
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/stm32mp1-clks.h>
#include <dt-bindings/reset/stm32mp1-resets.h>

/ {
	#address-cells = <1>;
	#size-cells = <1>;

	intc: interrupt-controller@a0021000 {
		compatible = "arm,cortex-a7-gic";
		#interrupt-cells = <3>;
		interrupt-controller;
		reg = <0xa0021000 0x1000>,
		      <0xa0022000 0x2000>;
	};

	clocks {
		clk_hse: clk-hse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <24000000>;
		};

		clk_hsi: clk-hsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <64000000>;
		};

		clk_lse: clk-lse {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32768>;
		};

		clk_lsi: clk-lsi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <32000>;
		};

		clk_csi: clk-csi {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <4000000>;
		};

		clk_i2s_ckin: i2s_ckin {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};

		clk_dsi_phy: ck_dsi_phy {
			#clock-cells = <0>;
			compatible = "fixed-clock";
			clock-frequency = <0>;
		};
	};

	soc {
		compatible = "simple-bus";
		#address-cells = <1>;
		#size-cells = <1>;
		interrupt-parent = <&intc>;
		ranges;

		usart2: serial@4000e000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000e000 0x400>;
			clocks = <&rcc USART2_K>;
			resets = <&rcc USART2_R>;
			status = "disabled";
		};

		usart3: serial@4000f000 {
			compatible = "st,stm32h7-uart";
			reg = <0x4000f000 0x400>;
			clocks = <&rcc USART3_K>;
			resets = <&rcc USART3_R>;
			status = "disabled";
		};

		uart4: serial@40010000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40010000 0x400>;
			clocks = <&rcc UART4_K>;
			resets = <&rcc UART4_R>;
			status = "disabled";
		};

		uart5: serial@40011000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40011000 0x400>;
			clocks = <&rcc UART5_K>;
			resets = <&rcc UART5_R>;
			status = "disabled";
		};


		uart7: serial@40018000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40018000 0x400>;
			clocks = <&rcc UART7_K>;
			resets = <&rcc UART7_R>;
			status = "disabled";
		};

		uart8: serial@40019000 {
			compatible = "st,stm32h7-uart";
			reg = <0x40019000 0x400>;
			clocks = <&rcc UART8_K>;
			resets = <&rcc UART8_R>;
			status = "disabled";
		};

		usart6: serial@44003000 {
			compatible = "st,stm32h7-uart";
			reg = <0x44003000 0x400>;
			clocks = <&rcc USART6_K>;
			resets = <&rcc USART6_R>;
			status = "disabled";
		};

		sdmmc3: sdmmc@48004000 {
			compatible = "st,stm32-sdmmc2";
			reg = <0x48004000 0x400>, <0x48005000 0x400>;
			clocks = <&rcc SDMMC3_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC3_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <120000000>;
			status = "disabled";
		};

		rcc: rcc@50000000 {
			compatible = "st,stm32mp1-rcc", "syscon";
			reg = <0x50000000 0x1000>;
			#clock-cells = <1>;
			#reset-cells = <1>;
			interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		};

		pwr: pwr@50001000 {
			compatible = "st,stm32mp1-pwr", "syscon", "simple-mfd";
			reg = <0x50001000 0x400>;
		};

		exti: interrupt-controller@5000d000 {
			compatible = "st,stm32mp1-exti", "syscon";
			interrupt-controller;
			#interrupt-cells = <2>;
			reg = <0x5000d000 0x400>;

			/* exti_pwr is an extra interrupt controller used for
			 * EXTI 55 to 60. It's mapped on pwr interrupt
			 * controller.
			 */
			exti_pwr: exti-pwr {
				interrupt-controller;
				#interrupt-cells = <2>;
				interrupt-parent = <&pwr>;
				st,irq-number = <6>;
			};
		};

		syscfg: syscon@50020000 {
			compatible = "st,stm32mp157-syscfg", "syscon";
			reg = <0x50020000 0x400>;
			clocks = <&rcc SYSCFG>;
		};

		rng1: rng@54003000 {
			compatible = "st,stm32-rng";
			reg = <0x54003000 0x400>;
			clocks = <&rcc RNG1_K>;
			resets = <&rcc RNG1_R>;
			status = "disabled";
		};

		fmc: nand-controller@58002000 {
			compatible = "st,stm32mp15-fmc2";
			reg = <0x58002000 0x1000>,
			      <0x80000000 0x1000>,
			      <0x88010000 0x1000>,
			      <0x88020000 0x1000>,
			      <0x81000000 0x1000>,
			      <0x89010000 0x1000>,
			      <0x89020000 0x1000>;
			clocks = <&rcc FMC_K>;
			resets = <&rcc FMC_R>;
			status = "disabled";
		};

		qspi: qspi@58003000 {
			compatible = "st,stm32f469-qspi";
			reg = <0x58003000 0x1000>, <0x70000000 0x10000000>;
			reg-names = "qspi", "qspi_mm";
			clocks = <&rcc QSPI_K>;
			resets = <&rcc QSPI_R>;
			status = "disabled";
		};

		sdmmc1: sdmmc@58005000 {
			compatible = "st,stm32-sdmmc2";
			reg = <0x58005000 0x1000>, <0x58006000 0x1000>;
			clocks = <&rcc SDMMC1_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC1_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <120000000>;
			status = "disabled";
		};

		sdmmc2: sdmmc@58007000 {
			compatible = "st,stm32-sdmmc2";
			reg = <0x58007000 0x1000>, <0x58008000 0x1000>;
			clocks = <&rcc SDMMC2_K>;
			clock-names = "apb_pclk";
			resets = <&rcc SDMMC2_R>;
			cap-sd-highspeed;
			cap-mmc-highspeed;
			max-frequency = <120000000>;
			status = "disabled";
		};

		iwdg2: watchdog@5a002000 {
			compatible = "st,stm32mp1-iwdg";
			reg = <0x5a002000 0x400>;
			clocks = <&rcc IWDG2>, <&rcc CK_LSI>;
			clock-names = "pclk", "lsi";
			status = "disabled";
		};

		usart1: serial@5c000000 {
			compatible = "st,stm32h7-uart";
			reg = <0x5c000000 0x400>;
			interrupt-names = "event", "wakeup";
			interrupts-extended = <&intc GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>,
					      <&exti 26 1>;
			clocks = <&rcc USART1_K>;
			resets = <&rcc USART1_R>;
			status = "disabled";
		};

		spi6: spi@5c001000 {
			#address-cells = <1>;
			#size-cells = <0>;
			compatible = "st,stm32h7-spi";
			reg = <0x5c001000 0x400>;
			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
			clocks = <&rcc SPI6_K>;
			resets = <&rcc SPI6_R>;
			status = "disabled";
		};

		i2c4: i2c@5c002000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x5c002000 0x400>;
			interrupt-names = "event", "error", "wakeup";
			interrupts-extended = <&intc GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
					      <&exti 24 1>;
			clocks = <&rcc I2C4_K>;
			resets = <&rcc I2C4_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

		rtc: rtc@5c004000 {
			compatible = "st,stm32mp1-rtc";
			reg = <0x5c004000 0x400>;
			clocks = <&rcc RTCAPB>, <&rcc RTC>;
			clock-names = "pclk", "rtc_ck";
			interrupts-extended = <&intc GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
					      <&exti 19 1>;
			status = "disabled";
		};

		bsec: nvmem@5c005000 {
			compatible = "st,stm32mp15-bsec";
			reg = <0x5c005000 0x400>;
			#address-cells = <1>;
			#size-cells = <1>;
			ts_cal1: calib@5c {
				reg = <0x5c 0x2>;
			};
			ts_cal2: calib@5e {
				reg = <0x5e 0x2>;
			};
		};

		i2c6: i2c@5c009000 {
			compatible = "st,stm32f7-i2c";
			reg = <0x5c009000 0x400>;
			interrupt-names = "event", "error", "wakeup";
			interrupts-extended = <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>,
					      <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
					      <&exti 54 1>;
			clocks = <&rcc I2C6_K>;
			resets = <&rcc I2C6_R>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};
	};
};