Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 10 | #include <arch.h> |
| 11 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <common/bl_common.h> |
| 13 | #include <common/debug.h> |
| 14 | #include <common/runtime_svc.h> |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 15 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <lib/el3_runtime/context_mgmt.h> |
| 17 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 18 | #include <mce.h> |
Varun Wadekar | a7c1ea7 | 2016-02-03 09:51:25 -0800 | [diff] [blame] | 19 | #include <memctrl.h> |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 20 | #include <t18x_ari.h> |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 21 | #include <tegra_private.h> |
| 22 | |
| 23 | /******************************************************************************* |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 24 | * Offset to read the ref_clk counter value |
| 25 | ******************************************************************************/ |
| 26 | #define REF_CLK_OFFSET 4 |
| 27 | |
| 28 | /******************************************************************************* |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 29 | * Tegra186 SiP SMCs |
| 30 | ******************************************************************************/ |
Varun Wadekar | 14f3957 | 2017-04-17 11:54:33 -0700 | [diff] [blame] | 31 | #define TEGRA_SIP_GET_ACTMON_CLK_COUNTERS 0xC2FFFE02 |
| 32 | #define TEGRA_SIP_MCE_CMD_ENTER_CSTATE 0xC2FFFF00 |
| 33 | #define TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO 0xC2FFFF01 |
| 34 | #define TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME 0xC2FFFF02 |
| 35 | #define TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS 0xC2FFFF03 |
| 36 | #define TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS 0xC2FFFF04 |
| 37 | #define TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED 0xC2FFFF05 |
| 38 | #define TEGRA_SIP_MCE_CMD_ONLINE_CORE 0xC2FFFF06 |
| 39 | #define TEGRA_SIP_MCE_CMD_CC3_CTRL 0xC2FFFF07 |
| 40 | #define TEGRA_SIP_MCE_CMD_ECHO_DATA 0xC2FFFF08 |
| 41 | #define TEGRA_SIP_MCE_CMD_READ_VERSIONS 0xC2FFFF09 |
| 42 | #define TEGRA_SIP_MCE_CMD_ENUM_FEATURES 0xC2FFFF0A |
| 43 | #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS 0xC2FFFF0B |
| 44 | #define TEGRA_SIP_MCE_CMD_ENUM_READ_MCA 0xC2FFFF0C |
| 45 | #define TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA 0xC2FFFF0D |
| 46 | #define TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE 0xC2FFFF0E |
| 47 | #define TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE 0xC2FFFF0F |
| 48 | #define TEGRA_SIP_MCE_CMD_ENABLE_LATIC 0xC2FFFF10 |
| 49 | #define TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ 0xC2FFFF11 |
| 50 | #define TEGRA_SIP_MCE_CMD_MISC_CCPLEX 0xC2FFFF12 |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 51 | |
| 52 | /******************************************************************************* |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 53 | * This function is responsible for handling all T186 SiP calls |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 54 | ******************************************************************************/ |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 55 | int plat_sip_handler(uint32_t smc_fid, |
| 56 | uint64_t x1, |
| 57 | uint64_t x2, |
| 58 | uint64_t x3, |
| 59 | uint64_t x4, |
Anthony Zhou | e5bd345 | 2017-03-01 12:47:37 +0800 | [diff] [blame] | 60 | const void *cookie, |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 61 | void *handle, |
| 62 | uint64_t flags) |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 63 | { |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 64 | int mce_ret; |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 65 | int impl, cpu; |
| 66 | uint32_t base, core_clk_ctr, ref_clk_ctr; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 67 | |
Varun Wadekar | 14f3957 | 2017-04-17 11:54:33 -0700 | [diff] [blame] | 68 | if (((smc_fid >> FUNCID_CC_SHIFT) & FUNCID_CC_MASK) == SMC_32) { |
| 69 | /* 32-bit function, clear top parameter bits */ |
| 70 | |
| 71 | x1 = (uint32_t)x1; |
| 72 | x2 = (uint32_t)x2; |
| 73 | x3 = (uint32_t)x3; |
| 74 | } |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 75 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 76 | /* |
Varun Wadekar | 14f3957 | 2017-04-17 11:54:33 -0700 | [diff] [blame] | 77 | * Convert SMC FID to SMC64, to support SMC32/SMC64 configurations |
| 78 | */ |
| 79 | smc_fid |= (SMC_64 << FUNCID_CC_SHIFT); |
| 80 | |
| 81 | switch (smc_fid) { |
| 82 | /* |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 83 | * Micro Coded Engine (MCE) commands reside in the 0x82FFFF00 - |
| 84 | * 0x82FFFFFF SiP SMC space |
| 85 | */ |
| 86 | case TEGRA_SIP_MCE_CMD_ENTER_CSTATE: |
| 87 | case TEGRA_SIP_MCE_CMD_UPDATE_CSTATE_INFO: |
| 88 | case TEGRA_SIP_MCE_CMD_UPDATE_CROSSOVER_TIME: |
| 89 | case TEGRA_SIP_MCE_CMD_READ_CSTATE_STATS: |
| 90 | case TEGRA_SIP_MCE_CMD_WRITE_CSTATE_STATS: |
| 91 | case TEGRA_SIP_MCE_CMD_IS_SC7_ALLOWED: |
| 92 | case TEGRA_SIP_MCE_CMD_CC3_CTRL: |
| 93 | case TEGRA_SIP_MCE_CMD_ECHO_DATA: |
| 94 | case TEGRA_SIP_MCE_CMD_READ_VERSIONS: |
| 95 | case TEGRA_SIP_MCE_CMD_ENUM_FEATURES: |
| 96 | case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE_TRBITS: |
| 97 | case TEGRA_SIP_MCE_CMD_ENUM_READ_MCA: |
| 98 | case TEGRA_SIP_MCE_CMD_ENUM_WRITE_MCA: |
| 99 | case TEGRA_SIP_MCE_CMD_ROC_FLUSH_CACHE: |
| 100 | case TEGRA_SIP_MCE_CMD_ROC_CLEAN_CACHE: |
Varun Wadekar | ad2824f | 2016-03-28 13:44:35 -0700 | [diff] [blame] | 101 | case TEGRA_SIP_MCE_CMD_ENABLE_LATIC: |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 102 | case TEGRA_SIP_MCE_CMD_UNCORE_PERFMON_REQ: |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 103 | case TEGRA_SIP_MCE_CMD_MISC_CCPLEX: |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 104 | |
| 105 | /* clean up the high bits */ |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 106 | smc_fid &= MCE_CMD_MASK; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 107 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 108 | /* execute the command and store the result */ |
| 109 | mce_ret = mce_command_handler(smc_fid, x1, x2, x3); |
Varun Wadekar | 14f3957 | 2017-04-17 11:54:33 -0700 | [diff] [blame] | 110 | write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X0, |
| 111 | (uint64_t)mce_ret); |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 112 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 113 | return 0; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 114 | |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 115 | /* |
| 116 | * This function ID reads the Activity monitor's core/ref clock |
| 117 | * counter values for a core/cluster. |
| 118 | * |
| 119 | * x1 = MPIDR of the target core |
| 120 | * x2 = MIDR of the target core |
| 121 | */ |
| 122 | case TEGRA_SIP_GET_ACTMON_CLK_COUNTERS: |
| 123 | |
| 124 | cpu = (uint32_t)x1 & MPIDR_CPU_MASK; |
| 125 | impl = ((uint32_t)x2 >> MIDR_IMPL_SHIFT) & MIDR_IMPL_MASK; |
| 126 | |
| 127 | /* sanity check target CPU number */ |
| 128 | if (cpu > PLATFORM_MAX_CPUS_PER_CLUSTER) |
| 129 | return -EINVAL; |
| 130 | |
| 131 | /* get the base address for the current CPU */ |
| 132 | base = (impl == DENVER_IMPL) ? TEGRA_DENVER_ACTMON_CTR_BASE : |
| 133 | TEGRA_ARM_ACTMON_CTR_BASE; |
| 134 | |
| 135 | /* read the clock counter values */ |
| 136 | core_clk_ctr = mmio_read_32(base + (8 * cpu)); |
| 137 | ref_clk_ctr = mmio_read_32(base + (8 * cpu) + REF_CLK_OFFSET); |
| 138 | |
| 139 | /* return the counter values as two different parameters */ |
Varun Wadekar | 14f3957 | 2017-04-17 11:54:33 -0700 | [diff] [blame] | 140 | write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X1, |
| 141 | (uint64_t)core_clk_ctr); |
| 142 | write_ctx_reg(get_gpregs_ctx(handle), CTX_GPREG_X2, |
| 143 | (uint64_t)ref_clk_ctr); |
Varun Wadekar | d64db96 | 2016-09-23 14:28:16 -0700 | [diff] [blame] | 144 | |
| 145 | return 0; |
| 146 | |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 147 | default: |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 148 | break; |
| 149 | } |
| 150 | |
Varun Wadekar | 59c3aa0 | 2015-09-09 11:33:08 +0530 | [diff] [blame] | 151 | return -ENOTSUP; |
Varun Wadekar | 921b906 | 2015-08-25 17:03:14 +0530 | [diff] [blame] | 152 | } |