Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 1 | /* |
Antonio Nino Diaz | 4b32e62 | 2018-08-16 16:52:57 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 7 | #include <assert.h> |
| 8 | #include <errno.h> |
| 9 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 10 | #include <arch.h> |
| 11 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 12 | #include <common/debug.h> |
| 13 | #include <drivers/delay_timer.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 14 | #include <denver.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 15 | #include <lib/mmio.h> |
| 16 | #include <plat/common/platform.h> |
| 17 | |
Varun Wadekar | b556828 | 2016-12-13 18:04:35 -0800 | [diff] [blame] | 18 | #include <mce_private.h> |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 19 | #include <t18x_ari.h> |
| 20 | |
| 21 | /******************************************************************************* |
| 22 | * Register offsets for ARI request/results |
| 23 | ******************************************************************************/ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 24 | #define ARI_REQUEST 0x0U |
| 25 | #define ARI_REQUEST_EVENT_MASK 0x4U |
| 26 | #define ARI_STATUS 0x8U |
| 27 | #define ARI_REQUEST_DATA_LO 0xCU |
| 28 | #define ARI_REQUEST_DATA_HI 0x10U |
| 29 | #define ARI_RESPONSE_DATA_LO 0x14U |
| 30 | #define ARI_RESPONSE_DATA_HI 0x18U |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 31 | |
| 32 | /* Status values for the current request */ |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 33 | #define ARI_REQ_PENDING 1U |
| 34 | #define ARI_REQ_ONGOING 3U |
| 35 | #define ARI_REQUEST_VALID_BIT (1U << 8) |
| 36 | #define ARI_EVT_MASK_STANDBYWFI_BIT (1U << 7) |
| 37 | |
| 38 | /* default timeout (ms) to wait for ARI completion */ |
| 39 | #define ARI_MAX_RETRY_COUNT 2000 |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 40 | |
| 41 | /******************************************************************************* |
| 42 | * ARI helper functions |
| 43 | ******************************************************************************/ |
| 44 | static inline uint32_t ari_read_32(uint32_t ari_base, uint32_t reg) |
| 45 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 46 | return mmio_read_32((uint64_t)ari_base + (uint64_t)reg); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 47 | } |
| 48 | |
| 49 | static inline void ari_write_32(uint32_t ari_base, uint32_t val, uint32_t reg) |
| 50 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 51 | mmio_write_32((uint64_t)ari_base + (uint64_t)reg, val); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 52 | } |
| 53 | |
| 54 | static inline uint32_t ari_get_request_low(uint32_t ari_base) |
| 55 | { |
| 56 | return ari_read_32(ari_base, ARI_REQUEST_DATA_LO); |
| 57 | } |
| 58 | |
| 59 | static inline uint32_t ari_get_request_high(uint32_t ari_base) |
| 60 | { |
| 61 | return ari_read_32(ari_base, ARI_REQUEST_DATA_HI); |
| 62 | } |
| 63 | |
| 64 | static inline uint32_t ari_get_response_low(uint32_t ari_base) |
| 65 | { |
| 66 | return ari_read_32(ari_base, ARI_RESPONSE_DATA_LO); |
| 67 | } |
| 68 | |
| 69 | static inline uint32_t ari_get_response_high(uint32_t ari_base) |
| 70 | { |
| 71 | return ari_read_32(ari_base, ARI_RESPONSE_DATA_HI); |
| 72 | } |
| 73 | |
| 74 | static inline void ari_clobber_response(uint32_t ari_base) |
| 75 | { |
| 76 | ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_LO); |
| 77 | ari_write_32(ari_base, 0, ARI_RESPONSE_DATA_HI); |
| 78 | } |
| 79 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 80 | static int32_t ari_request_wait(uint32_t ari_base, uint32_t evt_mask, uint32_t req, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 81 | uint32_t lo, uint32_t hi) |
| 82 | { |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 83 | uint32_t retries = ARI_MAX_RETRY_COUNT; |
| 84 | uint32_t status; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 85 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 86 | |
| 87 | /* program the request, event_mask, hi and lo registers */ |
| 88 | ari_write_32(ari_base, lo, ARI_REQUEST_DATA_LO); |
| 89 | ari_write_32(ari_base, hi, ARI_REQUEST_DATA_HI); |
| 90 | ari_write_32(ari_base, evt_mask, ARI_REQUEST_EVENT_MASK); |
| 91 | ari_write_32(ari_base, req | ARI_REQUEST_VALID_BIT, ARI_REQUEST); |
| 92 | |
| 93 | /* |
| 94 | * For commands that have an event trigger, we should bypass |
| 95 | * ARI_STATUS polling, since MCE is waiting for SW to trigger |
| 96 | * the event. |
| 97 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 98 | if (evt_mask != 0U) { |
| 99 | ret = 0; |
| 100 | } else { |
| 101 | /* For shutdown/reboot commands, we dont have to check for timeouts */ |
| 102 | if ((req == (uint32_t)TEGRA_ARI_MISC_CCPLEX) && |
| 103 | ((lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF) || |
| 104 | (lo == (uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT))) { |
| 105 | ret = 0; |
| 106 | } else { |
| 107 | /* |
| 108 | * Wait for the command response for not more than the timeout |
| 109 | */ |
| 110 | while (retries != 0U) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 111 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 112 | /* read the command status */ |
| 113 | status = ari_read_32(ari_base, ARI_STATUS); |
| 114 | if ((status & (ARI_REQ_ONGOING | ARI_REQ_PENDING)) == 0U) { |
| 115 | break; |
| 116 | } |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 117 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 118 | /* delay 1 ms */ |
| 119 | mdelay(1); |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 120 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 121 | /* decrement the retry count */ |
| 122 | retries--; |
| 123 | } |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 124 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 125 | /* assert if the command timed out */ |
| 126 | if (retries == 0U) { |
| 127 | ERROR("ARI request timed out: req %d on CPU %d\n", |
| 128 | req, plat_my_core_pos()); |
| 129 | assert(retries != 0U); |
| 130 | } |
| 131 | } |
Steven Kao | d346dca | 2016-12-23 16:17:18 +0800 | [diff] [blame] | 132 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 133 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 134 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 135 | } |
| 136 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 137 | int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 138 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 139 | int32_t ret = 0; |
| 140 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 141 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 142 | if ((state != TEGRA_ARI_CORE_C0) && |
| 143 | (state != TEGRA_ARI_CORE_C1) && |
| 144 | (state != TEGRA_ARI_CORE_C6) && |
| 145 | (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 146 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 147 | ret = EINVAL; |
| 148 | } else { |
| 149 | /* clean the previous response state */ |
| 150 | ari_clobber_response(ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 151 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 152 | /* Enter the cstate, to be woken up after wake_time (TSC ticks) */ |
| 153 | ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 154 | TEGRA_ARI_ENTER_CSTATE, state, wake_time); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 158 | } |
| 159 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 160 | int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccplex, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 161 | uint32_t system, uint8_t sys_state_force, uint32_t wake_mask, |
| 162 | uint8_t update_wake_mask) |
| 163 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 164 | uint32_t val = 0U; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 165 | |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 166 | /* clean the previous response state */ |
| 167 | ari_clobber_response(ari_base); |
| 168 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 169 | /* update CLUSTER_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 170 | if (cluster != 0U) { |
| 171 | val |= (cluster & (uint32_t)CLUSTER_CSTATE_MASK) | |
| 172 | (uint32_t)CLUSTER_CSTATE_UPDATE_BIT; |
| 173 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 174 | |
| 175 | /* update CCPLEX_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 176 | if (ccplex != 0U) { |
| 177 | val |= ((ccplex & (uint32_t)CCPLEX_CSTATE_MASK) << (uint32_t)CCPLEX_CSTATE_SHIFT) | |
| 178 | (uint32_t)CCPLEX_CSTATE_UPDATE_BIT; |
| 179 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 180 | |
| 181 | /* update SYSTEM_CSTATE? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 182 | if (system != 0U) { |
| 183 | val |= ((system & (uint32_t)SYSTEM_CSTATE_MASK) << (uint32_t)SYSTEM_CSTATE_SHIFT) | |
| 184 | (((uint32_t)sys_state_force << SYSTEM_CSTATE_FORCE_UPDATE_SHIFT) | |
| 185 | (uint32_t)SYSTEM_CSTATE_UPDATE_BIT); |
| 186 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 187 | |
| 188 | /* update wake mask value? */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 189 | if (update_wake_mask != 0U) { |
| 190 | val |= (uint32_t)CSTATE_WAKE_MASK_UPDATE_BIT; |
| 191 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 192 | |
| 193 | /* set the updated cstate info */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 194 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO, val, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 195 | wake_mask); |
| 196 | } |
| 197 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 198 | int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 199 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 200 | int32_t ret = 0; |
| 201 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 202 | /* sanity check crossover type */ |
| 203 | if ((type == TEGRA_ARI_CROSSOVER_C1_C6) || |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 204 | (type > TEGRA_ARI_CROSSOVER_CCP3_SC1)) { |
| 205 | ret = EINVAL; |
| 206 | } else { |
| 207 | /* clean the previous response state */ |
| 208 | ari_clobber_response(ari_base); |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 209 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 210 | /* update crossover threshold time */ |
| 211 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 212 | type, time); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 213 | } |
| 214 | |
| 215 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 216 | } |
| 217 | |
| 218 | uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state) |
| 219 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 220 | int32_t ret; |
| 221 | uint64_t result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 222 | |
| 223 | /* sanity check crossover type */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 224 | if (state == 0U) { |
| 225 | result = EINVAL; |
| 226 | } else { |
| 227 | /* clean the previous response state */ |
| 228 | ari_clobber_response(ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 229 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 230 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U); |
| 231 | if (ret != 0) { |
| 232 | result = EINVAL; |
| 233 | } else { |
| 234 | result = (uint64_t)ari_get_response_low(ari_base); |
| 235 | } |
| 236 | } |
| 237 | return result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 238 | } |
| 239 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 240 | int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 241 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 242 | /* clean the previous response state */ |
| 243 | ari_clobber_response(ari_base); |
| 244 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 245 | /* write the cstate stats */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 246 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 247 | stats); |
| 248 | } |
| 249 | |
| 250 | uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data) |
| 251 | { |
| 252 | uint64_t resp; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 253 | int32_t ret; |
| 254 | uint32_t local_data = data; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 255 | |
| 256 | /* clean the previous response state */ |
| 257 | ari_clobber_response(ari_base); |
| 258 | |
| 259 | /* ARI_REQUEST_DATA_HI is reserved for commands other than 'ECHO' */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 260 | if (cmd != TEGRA_ARI_MISC_ECHO) { |
| 261 | local_data = 0U; |
| 262 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 263 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 264 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data); |
| 265 | if (ret != 0) { |
| 266 | resp = (uint64_t)ret; |
| 267 | } else { |
| 268 | /* get the command response */ |
| 269 | resp = ari_get_response_low(ari_base); |
| 270 | resp |= ((uint64_t)ari_get_response_high(ari_base) << 32); |
| 271 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 272 | |
| 273 | return resp; |
| 274 | } |
| 275 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 276 | int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 277 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 278 | int32_t ret; |
| 279 | uint32_t result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 280 | |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 281 | /* clean the previous response state */ |
| 282 | ari_clobber_response(ari_base); |
| 283 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 284 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U, |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 285 | wake_time); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 286 | if (ret != 0) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 287 | ERROR("%s: failed (%d)\n", __func__, ret); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 288 | result = 0U; |
| 289 | } else { |
| 290 | result = ari_get_response_low(ari_base) & 0x1U; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /* 1 = CCx allowed, 0 = CCx not allowed */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 294 | return (int32_t)result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 295 | } |
| 296 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 297 | int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 298 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 299 | int32_t ret, result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 300 | |
| 301 | /* check for allowed power state */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 302 | if ((state != TEGRA_ARI_CORE_C0) && |
| 303 | (state != TEGRA_ARI_CORE_C1) && |
| 304 | (state != TEGRA_ARI_CORE_C6) && |
| 305 | (state != TEGRA_ARI_CORE_C7)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 306 | ERROR("%s: unknown cstate (%d)\n", __func__, state); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 307 | result = EINVAL; |
| 308 | } else { |
| 309 | /* clean the previous response state */ |
| 310 | ari_clobber_response(ari_base); |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 311 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 312 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state, |
| 313 | wake_time); |
| 314 | if (ret != 0) { |
| 315 | ERROR("%s: failed (%d)\n", __func__, ret); |
| 316 | result = 0; |
| 317 | } else { |
| 318 | /* 1 = SC7 allowed, 0 = SC7 not allowed */ |
| 319 | result = (ari_get_response_low(ari_base) != 0U) ? 1 : 0; |
| 320 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 321 | } |
| 322 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 323 | return result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 324 | } |
| 325 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 326 | int32_t ari_online_core(uint32_t ari_base, uint32_t core) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 327 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 328 | uint64_t cpu = read_mpidr() & (uint64_t)(MPIDR_CPU_MASK); |
Anthony Zhou | 0a01321 | 2017-05-08 20:17:08 +0800 | [diff] [blame] | 329 | uint64_t cluster = (read_mpidr() & ((uint64_t)(MPIDR_AFFLVL_MASK) << |
| 330 | (uint64_t)(MPIDR_AFFINITY_BITS))) >> |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 331 | (uint64_t)(MPIDR_AFFINITY_BITS); |
Anthony Zhou | 0a01321 | 2017-05-08 20:17:08 +0800 | [diff] [blame] | 332 | uint64_t impl = (read_midr() >> (uint64_t)MIDR_IMPL_SHIFT) & |
| 333 | (uint64_t)MIDR_IMPL_MASK; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 334 | int32_t ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 335 | |
| 336 | /* construct the current CPU # */ |
| 337 | cpu |= (cluster << 2); |
| 338 | |
| 339 | /* sanity check target core id */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 340 | if ((core >= MCE_CORE_ID_MAX) || (cpu == (uint64_t)core)) { |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 341 | ERROR("%s: unsupported core id (%d)\n", __func__, core); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 342 | ret = EINVAL; |
| 343 | } else { |
| 344 | /* |
| 345 | * The Denver cluster has 2 CPUs only - 0, 1. |
| 346 | */ |
| 347 | if ((impl == (uint32_t)DENVER_IMPL) && |
| 348 | ((core == 2U) || (core == 3U))) { |
| 349 | ERROR("%s: unknown core id (%d)\n", __func__, core); |
| 350 | ret = EINVAL; |
| 351 | } else { |
| 352 | /* clean the previous response state */ |
| 353 | ari_clobber_response(ari_base); |
| 354 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U); |
| 355 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 356 | } |
| 357 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 358 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 359 | } |
| 360 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 361 | int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t enable) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 362 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 363 | uint32_t val; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 364 | |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 365 | /* clean the previous response state */ |
| 366 | ari_clobber_response(ari_base); |
| 367 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 368 | /* |
| 369 | * If the enable bit is cleared, Auto-CC3 will be disabled by setting |
| 370 | * the SW visible voltage/frequency request registers for all non |
| 371 | * floorswept cores valid independent of StandbyWFI and disabling |
| 372 | * the IDLE voltage/frequency request register. If set, Auto-CC3 |
| 373 | * will be enabled by setting the ARM SW visible voltage/frequency |
| 374 | * request registers for all non floorswept cores to be enabled by |
| 375 | * StandbyWFI or the equivalent signal, and always keeping the IDLE |
| 376 | * voltage/frequency request register enabled. |
| 377 | */ |
| 378 | val = (((freq & MCE_AUTO_CC3_FREQ_MASK) << MCE_AUTO_CC3_FREQ_SHIFT) |\ |
| 379 | ((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 380 | ((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U)); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 381 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 382 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 383 | } |
| 384 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 385 | int32_t ari_reset_vector_update(uint32_t ari_base) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 386 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 387 | /* clean the previous response state */ |
| 388 | ari_clobber_response(ari_base); |
| 389 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 390 | /* |
| 391 | * Need to program the CPU reset vector one time during cold boot |
| 392 | * and SC7 exit |
| 393 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 394 | (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 395 | |
| 396 | return 0; |
| 397 | } |
| 398 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 399 | int32_t ari_roc_flush_cache_trbits(uint32_t ari_base) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 400 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 401 | /* clean the previous response state */ |
| 402 | ari_clobber_response(ari_base); |
| 403 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 404 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, |
| 405 | 0U, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 406 | } |
| 407 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 408 | int32_t ari_roc_flush_cache(uint32_t ari_base) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 409 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 410 | /* clean the previous response state */ |
| 411 | ari_clobber_response(ari_base); |
| 412 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 413 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, |
| 414 | 0U, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 415 | } |
| 416 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 417 | int32_t ari_roc_clean_cache(uint32_t ari_base) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 418 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 419 | /* clean the previous response state */ |
| 420 | ari_clobber_response(ari_base); |
| 421 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 422 | return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, |
| 423 | 0U, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 424 | } |
| 425 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 426 | uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 427 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 428 | uint64_t mca_arg_data, result = 0; |
| 429 | uint32_t resp_lo, resp_hi; |
| 430 | uint32_t mca_arg_err, mca_arg_finish; |
| 431 | int32_t ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 432 | |
| 433 | /* Set data (write) */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 434 | mca_arg_data = (data != NULL) ? *data : 0ULL; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 435 | |
| 436 | /* Set command */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 437 | ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO); |
| 438 | ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 439 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 440 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA, |
| 441 | (uint32_t)mca_arg_data, |
Antonio Nino Diaz | f94e40d | 2017-09-14 15:57:44 +0100 | [diff] [blame] | 442 | (uint32_t)(mca_arg_data >> 32U)); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 443 | if (ret == 0) { |
| 444 | resp_lo = ari_get_response_low(ari_base); |
| 445 | resp_hi = ari_get_response_high(ari_base); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 446 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 447 | mca_arg_err = resp_lo & MCA_ARG_ERROR_MASK; |
| 448 | mca_arg_finish = (resp_hi >> MCA_ARG_FINISH_SHIFT) & |
| 449 | MCA_ARG_FINISH_MASK; |
| 450 | |
| 451 | if (mca_arg_finish == 0U) { |
| 452 | result = (uint64_t)mca_arg_err; |
| 453 | } else { |
| 454 | if (data != NULL) { |
| 455 | resp_lo = ari_get_request_low(ari_base); |
| 456 | resp_hi = ari_get_request_high(ari_base); |
Antonio Nino Diaz | f94e40d | 2017-09-14 15:57:44 +0100 | [diff] [blame] | 457 | *data = ((uint64_t)resp_hi << 32U) | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 458 | (uint64_t)resp_lo; |
| 459 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 460 | } |
| 461 | } |
| 462 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 463 | return result; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 464 | } |
| 465 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 466 | int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx) |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 467 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 468 | int32_t ret = 0; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 469 | /* sanity check GSC ID */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 470 | if (gsc_idx > (uint32_t)TEGRA_ARI_GSC_VPR_IDX) { |
| 471 | ret = EINVAL; |
| 472 | } else { |
| 473 | /* clean the previous response state */ |
| 474 | ari_clobber_response(ari_base); |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 475 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 476 | /* |
| 477 | * The MCE code will read the GSC carveout value, corrseponding to |
| 478 | * the ID, from the MC registers and update the internal GSC registers |
| 479 | * of the CCPLEX. |
| 480 | */ |
| 481 | (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U); |
| 482 | } |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 483 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 484 | return ret; |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 485 | } |
| 486 | |
| 487 | void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx) |
| 488 | { |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 489 | /* clean the previous response state */ |
| 490 | ari_clobber_response(ari_base); |
| 491 | |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 492 | /* |
| 493 | * The MCE will shutdown or restart the entire system |
| 494 | */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 495 | (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U); |
Varun Wadekar | a0352ab | 2017-03-14 14:24:35 -0700 | [diff] [blame] | 496 | } |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 497 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 498 | int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req, |
| 499 | uint64_t *data) |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 500 | { |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 501 | int32_t ret, result; |
Anthony Zhou | 0a01321 | 2017-05-08 20:17:08 +0800 | [diff] [blame] | 502 | uint32_t val, req_status; |
| 503 | uint8_t req_cmd; |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 504 | |
| 505 | req_cmd = (uint8_t)(req >> UNCORE_PERFMON_CMD_SHIFT); |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 506 | |
Krishna Sitaraman | 282e583 | 2016-07-28 13:54:29 -0700 | [diff] [blame] | 507 | /* clean the previous response state */ |
| 508 | ari_clobber_response(ari_base); |
| 509 | |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 510 | /* sanity check input parameters */ |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 511 | if ((req_cmd == UNCORE_PERFMON_CMD_READ) && (data == NULL)) { |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 512 | ERROR("invalid parameters\n"); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 513 | result = EINVAL; |
| 514 | } else { |
| 515 | /* |
| 516 | * For "write" commands get the value that has to be written |
| 517 | * to the uncore perfmon registers |
| 518 | */ |
| 519 | val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ? |
Antonio Nino Diaz | f94e40d | 2017-09-14 15:57:44 +0100 | [diff] [blame] | 520 | (uint32_t)*data : 0U; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 521 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 522 | ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val, |
| 523 | (uint32_t)req); |
| 524 | if (ret != 0) { |
| 525 | result = ret; |
| 526 | } else { |
| 527 | /* read the command status value */ |
Anthony Zhou | 0a01321 | 2017-05-08 20:17:08 +0800 | [diff] [blame] | 528 | req_status = ari_get_response_high(ari_base) & |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 529 | UNCORE_PERFMON_RESP_STATUS_MASK; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 530 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 531 | /* |
| 532 | * For "read" commands get the data from the uncore |
| 533 | * perfmon registers |
| 534 | */ |
| 535 | req_status >>= UNCORE_PERFMON_RESP_STATUS_SHIFT; |
| 536 | if ((req_status == 0U) && (req_cmd == UNCORE_PERFMON_CMD_READ)) { |
| 537 | *data = ari_get_response_low(ari_base); |
| 538 | } |
| 539 | result = (int32_t)req_status; |
| 540 | } |
| 541 | } |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 542 | |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 543 | return result; |
Varun Wadekar | 4ff3e8d | 2016-04-29 10:40:02 -0700 | [diff] [blame] | 544 | } |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 545 | |
| 546 | void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value) |
| 547 | { |
| 548 | /* |
| 549 | * This invokes the ARI_MISC_CCPLEX commands. This can be |
| 550 | * used to enable/disable coresight clock gating. |
| 551 | */ |
| 552 | |
Rich Wiley | 24e9939 | 2017-01-04 10:45:44 -0800 | [diff] [blame] | 553 | if ((index > TEGRA_ARI_MISC_CCPLEX_EDBGREQ) || |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 554 | ((index == TEGRA_ARI_MISC_CCPLEX_CORESIGHT_CG_CTRL) && |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 555 | (value > 1U))) { |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 556 | ERROR("%s: invalid parameters \n", __func__); |
Anthony Zhou | 1ab3140 | 2017-03-06 16:06:45 +0800 | [diff] [blame] | 557 | } else { |
| 558 | /* clean the previous response state */ |
| 559 | ari_clobber_response(ari_base); |
| 560 | (void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value); |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 561 | } |
Krishna Sitaraman | b429d56 | 2016-07-19 16:36:13 -0700 | [diff] [blame] | 562 | } |