Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 33 | |
Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 34 | .globl bl1_entrypoint |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 35 | |
| 36 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 37 | /* ----------------------------------------------------- |
Jeenu Viswambharan | 2a30a75 | 2014-03-11 11:06:45 +0000 | [diff] [blame] | 38 | * bl1_entrypoint() is the entry point into the trusted |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 39 | * firmware code when a cpu is released from warm or |
| 40 | * cold reset. |
| 41 | * ----------------------------------------------------- |
| 42 | */ |
| 43 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 44 | func bl1_entrypoint |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 45 | /* --------------------------------------------- |
| 46 | * Perform any processor specific actions upon |
| 47 | * reset e.g. cache, tlb invalidations etc. |
| 48 | * --------------------------------------------- |
| 49 | */ |
| 50 | bl cpu_reset_handler |
| 51 | |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 52 | /* --------------------------------------------- |
| 53 | * Set the exception vector to something sane. |
| 54 | * --------------------------------------------- |
| 55 | */ |
Sandrine Bailleux | 4d05275 | 2014-03-24 10:24:08 +0000 | [diff] [blame] | 56 | adr x0, bl1_exceptions |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 57 | msr vbar_el3, x0 |
| 58 | |
Harry Liebel | 4f60368 | 2014-01-14 18:11:48 +0000 | [diff] [blame] | 59 | /* --------------------------------------------------------------------- |
| 60 | * The initial state of the Architectural feature trap register |
| 61 | * (CPTR_EL3) is unknown and it must be set to a known state. All |
| 62 | * feature traps are disabled. Some bits in this register are marked as |
| 63 | * Reserved and should not be modified. |
| 64 | * |
| 65 | * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 |
| 66 | * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. |
| 67 | * CPTR_EL3.TTA: This causes access to the Trace functionality to trap |
| 68 | * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register |
| 69 | * access to trace functionality is not supported, this bit is RES0. |
| 70 | * CPTR_EL3.TFP: This causes instructions that access the registers |
| 71 | * associated with Floating Point and Advanced SIMD execution to trap |
| 72 | * to EL3 when executed from any exception level, unless trapped to EL1 |
| 73 | * or EL2. |
| 74 | * --------------------------------------------------------------------- |
| 75 | */ |
| 76 | mrs x0, cptr_el3 |
| 77 | bic w0, w0, #TCPAC_BIT |
| 78 | bic w0, w0, #TTA_BIT |
| 79 | bic w0, w0, #TFP_BIT |
| 80 | msr cptr_el3, x0 |
| 81 | |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 82 | /* --------------------------------------------- |
| 83 | * Enable the instruction cache. |
| 84 | * --------------------------------------------- |
| 85 | */ |
| 86 | mrs x0, sctlr_el3 |
| 87 | orr x0, x0, #SCTLR_I_BIT |
| 88 | msr sctlr_el3, x0 |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 89 | isb |
| 90 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 91 | _wait_for_entrypoint: |
| 92 | /* --------------------------------------------- |
| 93 | * Find the type of reset and jump to handler |
| 94 | * if present. If the handler is null then it is |
| 95 | * a cold boot. The primary cpu will set up the |
| 96 | * platform while the secondaries wait for |
| 97 | * their turn to be woken up |
| 98 | * --------------------------------------------- |
| 99 | */ |
| 100 | bl read_mpidr |
| 101 | bl platform_get_entrypoint |
| 102 | cbnz x0, _do_warm_boot |
| 103 | bl read_mpidr |
| 104 | bl platform_is_primary_cpu |
| 105 | cbnz x0, _do_cold_boot |
| 106 | |
| 107 | /* --------------------------------------------- |
| 108 | * Perform any platform specific secondary cpu |
| 109 | * actions |
| 110 | * --------------------------------------------- |
| 111 | */ |
| 112 | bl plat_secondary_cold_boot_setup |
| 113 | b _wait_for_entrypoint |
| 114 | |
| 115 | _do_cold_boot: |
| 116 | /* --------------------------------------------- |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 117 | * Init C runtime environment. |
| 118 | * - Zero-initialise the NOBITS sections. |
| 119 | * There are 2 of them: |
| 120 | * - the .bss section; |
| 121 | * - the coherent memory section. |
| 122 | * - Copy the data section from BL1 image |
| 123 | * (stored in ROM) to the correct location |
| 124 | * in RAM. |
| 125 | * --------------------------------------------- |
| 126 | */ |
| 127 | ldr x0, =__BSS_START__ |
| 128 | ldr x1, =__BSS_SIZE__ |
| 129 | bl zeromem16 |
| 130 | |
| 131 | ldr x0, =__COHERENT_RAM_START__ |
| 132 | ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
| 133 | bl zeromem16 |
| 134 | |
| 135 | ldr x0, =__DATA_RAM_START__ |
| 136 | ldr x1, =__DATA_ROM_START__ |
| 137 | ldr x2, =__DATA_SIZE__ |
| 138 | bl memcpy16 |
| 139 | |
| 140 | /* --------------------------------------------- |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 141 | * Initialize platform and jump to our c-entry |
| 142 | * point for this type of reset |
| 143 | * --------------------------------------------- |
| 144 | */ |
| 145 | adr x0, bl1_main |
| 146 | bl platform_cold_boot_init |
| 147 | b _panic |
| 148 | |
| 149 | _do_warm_boot: |
| 150 | /* --------------------------------------------- |
| 151 | * Jump to BL31 for all warm boot init. |
| 152 | * --------------------------------------------- |
| 153 | */ |
| 154 | blr x0 |
| 155 | _panic: |
| 156 | b _panic |