Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2019 Marvell International Ltd. |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * https://spdx.org/licenses |
| 6 | */ |
| 7 | |
| 8 | #include <a8k_plat_def.h> |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 9 | #include <arch_helpers.h> |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 10 | #include <common/debug.h> |
| 11 | #include <lib/mmio.h> |
Grzegorz Jaszczyk | 7588ae2 | 2019-04-17 11:24:43 +0200 | [diff] [blame] | 12 | #include <mss_scp_bl2_format.h> |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 13 | |
| 14 | /* CONFI REGISTERS */ |
| 15 | #define MG_CM3_CONFI_BASE(CP) (MVEBU_CP_REGS_BASE(CP) + 0x100000) |
Grzegorz Jaszczyk | 7588ae2 | 2019-04-17 11:24:43 +0200 | [diff] [blame] | 16 | #define MG_CM3_SRAM_BASE(CP) MG_CM3_CONFI_BASE(CP) |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 17 | #define MG_CM3_CONFI_GLOB_CFG_REG(CP) (MG_CM3_CONFI_BASE(CP) + 0x2B500) |
| 18 | #define CM3_CPU_EN_BIT BIT(28) |
| 19 | #define MG_CM3_MG_INT_MFX_REG(CP) (MG_CM3_CONFI_BASE(CP) + 0x2B054) |
| 20 | #define CM3_SYS_RESET_BIT BIT(0) |
| 21 | |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 22 | #define MG_CM3_SHARED_MEM_BASE(CP) (MG_CM3_SRAM_BASE(CP) + 0x1FC00ULL) |
| 23 | |
Grzegorz Jaszczyk | 7588ae2 | 2019-04-17 11:24:43 +0200 | [diff] [blame] | 24 | #define MG_SRAM_SIZE 0x20000 /* 128KB */ |
| 25 | |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 26 | #define MG_ACK_TIMEOUT 10 |
| 27 | |
| 28 | /** |
| 29 | * struct ap_sharedmem_ctrl - used to pass information between the HOST and CM3 |
| 30 | * @init_done: Set by CM3 when ap_proces initialzied. Host check if CM3 set |
| 31 | * this flag to confirm that the process is running |
| 32 | * @lane_nr: Set by Host to mark which comphy lane should be configure. E.g.: |
| 33 | * - A8K development board uses comphy lane 2 for eth0 |
| 34 | * - CN913x development board uses comphy lane 4 for eth0 |
| 35 | */ |
| 36 | struct ap_sharedmem_ctrl { |
| 37 | uint32_t init_done; |
| 38 | uint32_t lane_nr; |
| 39 | }; |
| 40 | |
Grzegorz Jaszczyk | 7588ae2 | 2019-04-17 11:24:43 +0200 | [diff] [blame] | 41 | int mg_image_load(uintptr_t src_addr, uint32_t size, int cp_index) |
| 42 | { |
| 43 | uintptr_t mg_regs = MG_CM3_SRAM_BASE(cp_index); |
| 44 | |
| 45 | if (size > MG_SRAM_SIZE) { |
| 46 | ERROR("image is too big to fit into MG CM3 memory\n"); |
| 47 | return 1; |
| 48 | } |
| 49 | |
| 50 | NOTICE("Loading MG image from address 0x%lx Size 0x%x to MG at 0x%lx\n", |
| 51 | src_addr, size, mg_regs); |
| 52 | |
| 53 | /* Copy image to MG CM3 SRAM */ |
| 54 | memcpy((void *)mg_regs, (void *)src_addr, size); |
| 55 | |
| 56 | /* Don't release MG CM3 from reset - it will be done by next step |
| 57 | * bootloader (e.g. U-Boot), when appriopriate device-tree setup (which |
| 58 | * has enabeld 802.3. auto-neg) will be choosen. |
| 59 | */ |
| 60 | |
| 61 | return 0; |
| 62 | } |
| 63 | |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 64 | void mg_start_ap_fw(int cp_nr, uint8_t comphy_index) |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 65 | { |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 66 | volatile struct ap_sharedmem_ctrl *ap_shared_ctrl = |
| 67 | (void *)MG_CM3_SHARED_MEM_BASE(cp_nr); |
| 68 | int timeout = MG_ACK_TIMEOUT; |
| 69 | |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 70 | if (mmio_read_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr)) & CM3_CPU_EN_BIT) { |
| 71 | VERBOSE("cm3 already running\n"); |
| 72 | return; /* cm3 already running */ |
| 73 | } |
| 74 | |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 75 | /* |
| 76 | * Mark which comphy lane should be used - it will be read via shared |
| 77 | * mem by ap process |
| 78 | */ |
| 79 | ap_shared_ctrl->lane_nr = comphy_index; |
| 80 | /* Make sure it took place before enabling cm3 */ |
| 81 | dmbst(); |
| 82 | |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 83 | mmio_setbits_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr), CM3_CPU_EN_BIT); |
| 84 | mmio_setbits_32(MG_CM3_MG_INT_MFX_REG(cp_nr), CM3_SYS_RESET_BIT); |
| 85 | |
Grzegorz Jaszczyk | c30b886 | 2019-06-18 14:43:02 +0200 | [diff] [blame] | 86 | /* Check for ap process initialization by fw */ |
| 87 | while (ap_shared_ctrl->init_done != 1 && timeout--) |
| 88 | VERBOSE("Waiting for ap process ack, timeout %d\n", timeout); |
| 89 | |
| 90 | if (timeout == 0) { |
| 91 | ERROR("AP process failed, disabling cm3\n"); |
| 92 | mmio_clrbits_32(MG_CM3_MG_INT_MFX_REG(cp_nr), |
| 93 | CM3_SYS_RESET_BIT); |
| 94 | mmio_clrbits_32(MG_CM3_CONFI_GLOB_CFG_REG(cp_nr), |
| 95 | CM3_CPU_EN_BIT); |
| 96 | } |
Grzegorz Jaszczyk | 65b9afa | 2019-04-12 16:53:49 +0200 | [diff] [blame] | 97 | } |