Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 1 | /* |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 2 | * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved. |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 5 | */ |
| 6 | |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 7 | #include <arch_helpers.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | #include <common/bl_common.h> |
| 9 | #include <lib/xlat_tables/xlat_tables_v2.h> |
| 10 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 11 | #include <tegra_def.h> |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 12 | #include <tegra_private.h> |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 13 | |
Varun Wadekar | a78bb1b | 2015-08-07 10:03:00 +0530 | [diff] [blame] | 14 | /******************************************************************************* |
| 15 | * The Tegra power domain tree has a single system level power domain i.e. a |
| 16 | * single root node. The first entry in the power domain descriptor specifies |
| 17 | * the number of power domains at the highest power level. |
| 18 | ******************************************************************************* |
| 19 | */ |
| 20 | const unsigned char tegra_power_domain_tree_desc[] = { |
| 21 | /* No of root nodes */ |
| 22 | 1, |
| 23 | /* No of clusters */ |
| 24 | PLATFORM_CLUSTER_COUNT, |
| 25 | /* No of CPU cores */ |
| 26 | PLATFORM_CORE_COUNT, |
| 27 | }; |
| 28 | |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 29 | /* sets of MMIO ranges setup */ |
| 30 | #define MMIO_RANGE_0_ADDR 0x50000000 |
| 31 | #define MMIO_RANGE_1_ADDR 0x60000000 |
| 32 | #define MMIO_RANGE_2_ADDR 0x70000000 |
| 33 | #define MMIO_RANGE_SIZE 0x200000 |
| 34 | |
| 35 | /* |
| 36 | * Table of regions to map using the MMU. |
| 37 | */ |
| 38 | static const mmap_region_t tegra_mmap[] = { |
| 39 | MAP_REGION_FLAT(MMIO_RANGE_0_ADDR, MMIO_RANGE_SIZE, |
| 40 | MT_DEVICE | MT_RW | MT_SECURE), |
| 41 | MAP_REGION_FLAT(MMIO_RANGE_1_ADDR, MMIO_RANGE_SIZE, |
| 42 | MT_DEVICE | MT_RW | MT_SECURE), |
| 43 | MAP_REGION_FLAT(MMIO_RANGE_2_ADDR, MMIO_RANGE_SIZE, |
| 44 | MT_DEVICE | MT_RW | MT_SECURE), |
| 45 | {0} |
| 46 | }; |
| 47 | |
| 48 | /******************************************************************************* |
| 49 | * Set up the pagetables as per the platform memory map & initialize the MMU |
| 50 | ******************************************************************************/ |
| 51 | const mmap_region_t *plat_get_mmio_map(void) |
| 52 | { |
| 53 | /* MMIO space */ |
| 54 | return tegra_mmap; |
| 55 | } |
| 56 | |
Antonio Nino Diaz | e82e29c | 2016-05-19 10:00:28 +0100 | [diff] [blame] | 57 | unsigned int plat_get_syscnt_freq2(void) |
Varun Wadekar | 0f3baa0 | 2015-07-16 11:36:33 +0530 | [diff] [blame] | 58 | { |
| 59 | return 12000000; |
| 60 | } |
Varun Wadekar | d2014c6 | 2015-10-29 10:37:28 +0530 | [diff] [blame] | 61 | |
| 62 | /******************************************************************************* |
| 63 | * Maximum supported UART controllers |
| 64 | ******************************************************************************/ |
| 65 | #define TEGRA132_MAX_UART_PORTS 5 |
| 66 | |
| 67 | /******************************************************************************* |
| 68 | * This variable holds the UART port base addresses |
| 69 | ******************************************************************************/ |
| 70 | static uint32_t tegra132_uart_addresses[TEGRA132_MAX_UART_PORTS + 1] = { |
| 71 | 0, /* undefined - treated as an error case */ |
| 72 | TEGRA_UARTA_BASE, |
| 73 | TEGRA_UARTB_BASE, |
| 74 | TEGRA_UARTC_BASE, |
| 75 | TEGRA_UARTD_BASE, |
| 76 | TEGRA_UARTE_BASE, |
| 77 | }; |
| 78 | |
| 79 | /******************************************************************************* |
| 80 | * Retrieve the UART controller base to be used as the console |
| 81 | ******************************************************************************/ |
| 82 | uint32_t plat_get_console_from_id(int id) |
| 83 | { |
| 84 | if (id > TEGRA132_MAX_UART_PORTS) |
| 85 | return 0; |
| 86 | |
| 87 | return tegra132_uart_addresses[id]; |
| 88 | } |
Varun Wadekar | b7b4575 | 2015-12-28 14:55:41 -0800 | [diff] [blame] | 89 | |
| 90 | /******************************************************************************* |
| 91 | * Initialize the GIC and SGIs |
| 92 | ******************************************************************************/ |
| 93 | void plat_gic_setup(void) |
| 94 | { |
| 95 | tegra_gic_setup(NULL, 0); |
| 96 | } |