blob: f5d4b2f38ba03d90f5f16ba75979e81f2303a54e [file] [log] [blame]
Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautier2f974232020-09-17 12:25:05 +02002 * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010025#include <stm32mp_shres_helpers.h>
Yann Gautierc7374052019-06-04 18:02:37 +020026#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010027#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010028#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010029#endif
30
Yann Gautier0ed7b2a2021-05-19 18:48:16 +020031#if !STM32MP_USE_STM32IMAGE
32#include "stm32mp1_fip_def.h"
33#else /* STM32MP_USE_STM32IMAGE */
34#include "stm32mp1_stm32image_def.h"
35#endif /* STM32MP_USE_STM32IMAGE */
36
Yann Gautier4b0c72a2018-07-16 10:54:09 +020037/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020038 * CHIP ID
39 ******************************************************************************/
Yann Gautiera0a6ff62021-05-10 16:05:18 +020040#define STM32MP1_CHIP_ID U(0x500)
41
Yann Gautierc7374052019-06-04 18:02:37 +020042#define STM32MP157C_PART_NB U(0x05000000)
43#define STM32MP157A_PART_NB U(0x05000001)
44#define STM32MP153C_PART_NB U(0x05000024)
45#define STM32MP153A_PART_NB U(0x05000025)
46#define STM32MP151C_PART_NB U(0x0500002E)
47#define STM32MP151A_PART_NB U(0x0500002F)
Lionel Debieve7b64e3e2019-05-17 16:01:18 +020048#define STM32MP157F_PART_NB U(0x05000080)
49#define STM32MP157D_PART_NB U(0x05000081)
50#define STM32MP153F_PART_NB U(0x050000A4)
51#define STM32MP153D_PART_NB U(0x050000A5)
52#define STM32MP151F_PART_NB U(0x050000AE)
53#define STM32MP151D_PART_NB U(0x050000AF)
Yann Gautierc7374052019-06-04 18:02:37 +020054
55#define STM32MP1_REV_B U(0x2000)
Lionel Debieve2d64b532019-06-25 10:40:37 +020056#define STM32MP1_REV_Z U(0x2001)
Yann Gautierc7374052019-06-04 18:02:37 +020057
58/*******************************************************************************
59 * PACKAGE ID
60 ******************************************************************************/
61#define PKG_AA_LFBGA448 U(4)
62#define PKG_AB_LFBGA354 U(3)
63#define PKG_AC_TFBGA361 U(2)
64#define PKG_AD_TFBGA257 U(1)
65
66/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020067 * STM32MP1 memory map related constants
68 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020069#define STM32MP_ROM_BASE U(0x00000000)
70#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020071
Yann Gautiera2e2a302019-02-14 11:13:39 +010072#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
73#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020074
Etienne Carriere72369b12019-12-08 08:17:56 +010075#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
76#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
77 STM32MP_SYSRAM_SIZE - \
78 STM32MP_NS_SYSRAM_SIZE)
79
Etienne Carriere34f0e932020-07-16 17:36:18 +020080#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
81#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
82
Etienne Carriere72369b12019-12-08 08:17:56 +010083#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
84#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
85 STM32MP_NS_SYSRAM_SIZE)
86
Yann Gautier4b0c72a2018-07-16 10:54:09 +020087/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010088#define STM32MP_DDR_BASE U(0xC0000000)
89#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020090
91/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -070092#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +020093enum ddr_type {
94 STM32MP_DDR3,
95 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +020096 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +020097};
98#endif
99
100/* Section used inside TF binaries */
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200101#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200102/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100103#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200104
Etienne Carriere72369b12019-12-08 08:17:56 +0100105#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100106 STM32MP_PARAM_LOAD_SIZE + \
107 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200108
Etienne Carriere72369b12019-12-08 08:17:56 +0100109#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100110 (STM32MP_PARAM_LOAD_SIZE + \
111 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200112
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200113/* BL2 and BL32/sp_min require 4 tables */
114#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200115
116/*
117 * MAX_MMAP_REGIONS is usually:
118 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
119 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200120#if defined(IMAGE_BL2)
121 #define MAX_MMAP_REGIONS 11
122#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200123
Yann Gautiera2e2a302019-02-14 11:13:39 +0100124#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier0ed7b2a2021-05-19 18:48:16 +0200125#define STM32MP_BL33_MAX_SIZE U(0x400000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200126
Lionel Debieve402a46b2019-11-04 12:28:15 +0100127/* Define maximum page size for NAND devices */
128#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
129
130/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200131 * STM32MP1 device/io map related constants (used for MMU)
132 ******************************************************************************/
133#define STM32MP1_DEVICE1_BASE U(0x40000000)
134#define STM32MP1_DEVICE1_SIZE U(0x40000000)
135
136#define STM32MP1_DEVICE2_BASE U(0x80000000)
137#define STM32MP1_DEVICE2_SIZE U(0x40000000)
138
139/*******************************************************************************
140 * STM32MP1 RCC
141 ******************************************************************************/
142#define RCC_BASE U(0x50000000)
143
144/*******************************************************************************
145 * STM32MP1 PWR
146 ******************************************************************************/
147#define PWR_BASE U(0x50001000)
148
149/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100150 * STM32MP1 GPIO
151 ******************************************************************************/
152#define GPIOA_BASE U(0x50002000)
153#define GPIOB_BASE U(0x50003000)
154#define GPIOC_BASE U(0x50004000)
155#define GPIOD_BASE U(0x50005000)
156#define GPIOE_BASE U(0x50006000)
157#define GPIOF_BASE U(0x50007000)
158#define GPIOG_BASE U(0x50008000)
159#define GPIOH_BASE U(0x50009000)
160#define GPIOI_BASE U(0x5000A000)
161#define GPIOJ_BASE U(0x5000B000)
162#define GPIOK_BASE U(0x5000C000)
163#define GPIOZ_BASE U(0x54004000)
164#define GPIO_BANK_OFFSET U(0x1000)
165
166/* Bank IDs used in GPIO driver API */
167#define GPIO_BANK_A U(0)
168#define GPIO_BANK_B U(1)
169#define GPIO_BANK_C U(2)
170#define GPIO_BANK_D U(3)
171#define GPIO_BANK_E U(4)
172#define GPIO_BANK_F U(5)
173#define GPIO_BANK_G U(6)
174#define GPIO_BANK_H U(7)
175#define GPIO_BANK_I U(8)
176#define GPIO_BANK_J U(9)
177#define GPIO_BANK_K U(10)
178#define GPIO_BANK_Z U(25)
179
180#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
181
182/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200183 * STM32MP1 UART
184 ******************************************************************************/
185#define USART1_BASE U(0x5C000000)
186#define USART2_BASE U(0x4000E000)
187#define USART3_BASE U(0x4000F000)
188#define UART4_BASE U(0x40010000)
189#define UART5_BASE U(0x40011000)
190#define USART6_BASE U(0x44003000)
191#define UART7_BASE U(0x40018000)
192#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100193#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100194
195/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100196#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100197/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100198#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100199#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
200#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
201#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
202#define DEBUG_UART_TX_GPIO_PORT 11
203#define DEBUG_UART_TX_GPIO_ALTERNATE 6
204#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
205#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
206#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
207#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier5c84e742020-09-14 17:21:59 +0200208#define DEBUG_UART_RST_REG RCC_APB1RSTSETR
209#define DEBUG_UART_RST_BIT RCC_APB1RSTSETR_UART4RST
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200210
211/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200212 * STM32MP1 ETZPC
213 ******************************************************************************/
214#define STM32MP1_ETZPC_BASE U(0x5C007000)
215
216/* ETZPC TZMA IDs */
217#define STM32MP1_ETZPC_TZMA_ROM U(0)
218#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
219
220#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
221
222/* ETZPC DECPROT IDs */
223#define STM32MP1_ETZPC_STGENC_ID 0
224#define STM32MP1_ETZPC_BKPSRAM_ID 1
225#define STM32MP1_ETZPC_IWDG1_ID 2
226#define STM32MP1_ETZPC_USART1_ID 3
227#define STM32MP1_ETZPC_SPI6_ID 4
228#define STM32MP1_ETZPC_I2C4_ID 5
229#define STM32MP1_ETZPC_RNG1_ID 7
230#define STM32MP1_ETZPC_HASH1_ID 8
231#define STM32MP1_ETZPC_CRYP1_ID 9
232#define STM32MP1_ETZPC_DDRCTRL_ID 10
233#define STM32MP1_ETZPC_DDRPHYC_ID 11
234#define STM32MP1_ETZPC_I2C6_ID 12
235#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
236
237#define STM32MP1_ETZPC_TIM2_ID 16
238#define STM32MP1_ETZPC_TIM3_ID 17
239#define STM32MP1_ETZPC_TIM4_ID 18
240#define STM32MP1_ETZPC_TIM5_ID 19
241#define STM32MP1_ETZPC_TIM6_ID 20
242#define STM32MP1_ETZPC_TIM7_ID 21
243#define STM32MP1_ETZPC_TIM12_ID 22
244#define STM32MP1_ETZPC_TIM13_ID 23
245#define STM32MP1_ETZPC_TIM14_ID 24
246#define STM32MP1_ETZPC_LPTIM1_ID 25
247#define STM32MP1_ETZPC_WWDG1_ID 26
248#define STM32MP1_ETZPC_SPI2_ID 27
249#define STM32MP1_ETZPC_SPI3_ID 28
250#define STM32MP1_ETZPC_SPDIFRX_ID 29
251#define STM32MP1_ETZPC_USART2_ID 30
252#define STM32MP1_ETZPC_USART3_ID 31
253#define STM32MP1_ETZPC_UART4_ID 32
254#define STM32MP1_ETZPC_UART5_ID 33
255#define STM32MP1_ETZPC_I2C1_ID 34
256#define STM32MP1_ETZPC_I2C2_ID 35
257#define STM32MP1_ETZPC_I2C3_ID 36
258#define STM32MP1_ETZPC_I2C5_ID 37
259#define STM32MP1_ETZPC_CEC_ID 38
260#define STM32MP1_ETZPC_DAC_ID 39
261#define STM32MP1_ETZPC_UART7_ID 40
262#define STM32MP1_ETZPC_UART8_ID 41
263#define STM32MP1_ETZPC_MDIOS_ID 44
264#define STM32MP1_ETZPC_TIM1_ID 48
265#define STM32MP1_ETZPC_TIM8_ID 49
266#define STM32MP1_ETZPC_USART6_ID 51
267#define STM32MP1_ETZPC_SPI1_ID 52
268#define STM32MP1_ETZPC_SPI4_ID 53
269#define STM32MP1_ETZPC_TIM15_ID 54
270#define STM32MP1_ETZPC_TIM16_ID 55
271#define STM32MP1_ETZPC_TIM17_ID 56
272#define STM32MP1_ETZPC_SPI5_ID 57
273#define STM32MP1_ETZPC_SAI1_ID 58
274#define STM32MP1_ETZPC_SAI2_ID 59
275#define STM32MP1_ETZPC_SAI3_ID 60
276#define STM32MP1_ETZPC_DFSDM_ID 61
277#define STM32MP1_ETZPC_TT_FDCAN_ID 62
278#define STM32MP1_ETZPC_LPTIM2_ID 64
279#define STM32MP1_ETZPC_LPTIM3_ID 65
280#define STM32MP1_ETZPC_LPTIM4_ID 66
281#define STM32MP1_ETZPC_LPTIM5_ID 67
282#define STM32MP1_ETZPC_SAI4_ID 68
283#define STM32MP1_ETZPC_VREFBUF_ID 69
284#define STM32MP1_ETZPC_DCMI_ID 70
285#define STM32MP1_ETZPC_CRC2_ID 71
286#define STM32MP1_ETZPC_ADC_ID 72
287#define STM32MP1_ETZPC_HASH2_ID 73
288#define STM32MP1_ETZPC_RNG2_ID 74
289#define STM32MP1_ETZPC_CRYP2_ID 75
290#define STM32MP1_ETZPC_SRAM1_ID 80
291#define STM32MP1_ETZPC_SRAM2_ID 81
292#define STM32MP1_ETZPC_SRAM3_ID 82
293#define STM32MP1_ETZPC_SRAM4_ID 83
294#define STM32MP1_ETZPC_RETRAM_ID 84
295#define STM32MP1_ETZPC_OTG_ID 85
296#define STM32MP1_ETZPC_SDMMC3_ID 86
297#define STM32MP1_ETZPC_DLYBSD3_ID 87
298#define STM32MP1_ETZPC_DMA1_ID 88
299#define STM32MP1_ETZPC_DMA2_ID 89
300#define STM32MP1_ETZPC_DMAMUX_ID 90
301#define STM32MP1_ETZPC_FMC_ID 91
302#define STM32MP1_ETZPC_QSPI_ID 92
303#define STM32MP1_ETZPC_DLYBQ_ID 93
304#define STM32MP1_ETZPC_ETH_ID 94
305#define STM32MP1_ETZPC_RSV_ID 95
306
307#define STM32MP_ETZPC_MAX_ID 96
308
309/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200310 * STM32MP1 TZC (TZ400)
311 ******************************************************************************/
312#define STM32MP1_TZC_BASE U(0x5C006000)
313
Yann Gautier2f974232020-09-17 12:25:05 +0200314#define STM32MP1_FILTER_BIT_ALL (TZC_400_REGION_ATTR_FILTER_BIT(0) | \
315 TZC_400_REGION_ATTR_FILTER_BIT(1))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200316
317/*******************************************************************************
318 * STM32MP1 SDMMC
319 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100320#define STM32MP_SDMMC1_BASE U(0x58005000)
321#define STM32MP_SDMMC2_BASE U(0x58007000)
322#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200323
Yann Gautier4baf5822019-05-09 13:25:52 +0200324#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
325#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
326#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
327#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
328#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200329
330/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100331 * STM32MP1 BSEC / OTP
332 ******************************************************************************/
333#define STM32MP1_OTP_MAX_ID 0x5FU
334#define STM32MP1_UPPER_OTP_START 0x20U
335
336#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
337
338/* OTP offsets */
339#define DATA0_OTP U(0)
Yann Gautierc7374052019-06-04 18:02:37 +0200340#define PART_NUMBER_OTP U(1)
Lionel Debieve402a46b2019-11-04 12:28:15 +0100341#define NAND_OTP U(9)
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200342#define UID0_OTP U(13)
343#define UID1_OTP U(14)
344#define UID2_OTP U(15)
Yann Gautierc7374052019-06-04 18:02:37 +0200345#define PACKAGE_OTP U(16)
Yann Gautier3edc7c32019-05-20 19:17:08 +0200346#define HW2_OTP U(18)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100347
348/* OTP mask */
349/* DATA0 */
350#define DATA0_OTP_SECURED BIT(6)
351
Yann Gautierc7374052019-06-04 18:02:37 +0200352/* PART NUMBER */
353#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
354#define PART_NUMBER_OTP_PART_SHIFT 0
355
356/* PACKAGE */
357#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
358#define PACKAGE_OTP_PKG_SHIFT 27
359
Yann Gautier091eab52019-06-04 18:06:34 +0200360/* IWDG OTP */
361#define HW2_OTP_IWDG_HW_POS U(3)
362#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
363#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
364
Yann Gautier3edc7c32019-05-20 19:17:08 +0200365/* HW2 OTP */
366#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
367
Lionel Debieve402a46b2019-11-04 12:28:15 +0100368/* NAND OTP */
369/* NAND parameter storage flag */
370#define NAND_PARAM_STORED_IN_OTP BIT(31)
371
372/* NAND page size in bytes */
373#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
374#define NAND_PAGE_SIZE_SHIFT 29
375#define NAND_PAGE_SIZE_2K U(0)
376#define NAND_PAGE_SIZE_4K U(1)
377#define NAND_PAGE_SIZE_8K U(2)
378
379/* NAND block size in pages */
380#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
381#define NAND_BLOCK_SIZE_SHIFT 27
382#define NAND_BLOCK_SIZE_64_PAGES U(0)
383#define NAND_BLOCK_SIZE_128_PAGES U(1)
384#define NAND_BLOCK_SIZE_256_PAGES U(2)
385
386/* NAND number of block (in unit of 256 blocs) */
387#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
388#define NAND_BLOCK_NB_SHIFT 19
389#define NAND_BLOCK_NB_UNIT U(256)
390
391/* NAND bus width in bits */
392#define NAND_WIDTH_MASK BIT(18)
393#define NAND_WIDTH_SHIFT 18
394
395/* NAND number of ECC bits per 512 bytes */
396#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
397#define NAND_ECC_BIT_NB_SHIFT 15
398#define NAND_ECC_BIT_NB_UNSET U(0)
399#define NAND_ECC_BIT_NB_1_BITS U(1)
400#define NAND_ECC_BIT_NB_4_BITS U(2)
401#define NAND_ECC_BIT_NB_8_BITS U(3)
402#define NAND_ECC_ON_DIE U(4)
403
Lionel Debieve186b0462019-09-24 18:30:12 +0200404/* NAND number of planes */
405#define NAND_PLANE_BIT_NB_MASK BIT(14)
406
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200407/* UID OTP */
408#define UID_WORD_NB U(3)
409
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100410/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200411 * STM32MP1 TAMP
412 ******************************************************************************/
413#define TAMP_BASE U(0x5C00A000)
414#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
415
Julius Werner53456fc2019-07-09 13:49:11 -0700416#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Yann Gautier41934662018-07-20 11:36:05 +0200417static inline uint32_t tamp_bkpr(uint32_t idx)
418{
419 return TAMP_BKP_REGISTER_BASE + (idx << 2);
420}
421#endif
422
423/*******************************************************************************
Patrick Delaunayf12b7452021-06-30 17:06:19 +0200424 * STM32MP1 USB
425 ******************************************************************************/
426#define USB_OTG_BASE U(0x49000000)
427
428/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200429 * STM32MP1 DDRCTRL
430 ******************************************************************************/
431#define DDRCTRL_BASE U(0x5A003000)
432
433/*******************************************************************************
434 * STM32MP1 DDRPHYC
435 ******************************************************************************/
436#define DDRPHYC_BASE U(0x5A004000)
437
438/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200439 * STM32MP1 IWDG
440 ******************************************************************************/
441#define IWDG_MAX_INSTANCE U(2)
442#define IWDG1_INST U(0)
443#define IWDG2_INST U(1)
444
445#define IWDG1_BASE U(0x5C003000)
446#define IWDG2_BASE U(0x5A002000)
447
448/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200449 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200450 ******************************************************************************/
Yann Gautiera18f61b2020-05-05 17:58:40 +0200451#define BSEC_BASE U(0x5C005000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200452#define CRYP1_BASE U(0x54001000)
Yann Gautier091eab52019-06-04 18:06:34 +0200453#define DBGMCU_BASE U(0x50081000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200454#define HASH1_BASE U(0x54002000)
455#define I2C4_BASE U(0x5C002000)
456#define I2C6_BASE U(0x5c009000)
457#define RNG1_BASE U(0x54003000)
458#define RTC_BASE U(0x5c004000)
459#define SPI6_BASE U(0x5c001000)
Yann Gautiera18f61b2020-05-05 17:58:40 +0200460#define STGEN_BASE U(0x5c008000)
461#define SYSCFG_BASE U(0x50020000)
Yann Gautier091eab52019-06-04 18:06:34 +0200462
463/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100464 * Device Tree defines
465 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200466#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Yann Gautier091eab52019-06-04 18:06:34 +0200467#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200468#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Yann Gautier4d429472019-02-14 11:15:20 +0100469#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
470
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200471#endif /* STM32MP1_DEF_H */