Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 1 | /* |
Soby Mathew | 3700a92 | 2015-07-13 11:21:11 +0100 | [diff] [blame] | 2 | * Copyright (c) 2014-2015, ARM Limited and Contributors. All rights reserved. |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #ifndef __CPU_DATA_H__ |
| 32 | #define __CPU_DATA_H__ |
| 33 | |
| 34 | /* Offsets for the cpu_data structure */ |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 35 | #define CPU_DATA_CRASH_BUF_OFFSET 0x18 |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 36 | #if CRASH_REPORTING |
| 37 | #define CPU_DATA_LOG2SIZE 7 |
| 38 | #else |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 39 | #define CPU_DATA_LOG2SIZE 6 |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 40 | #endif |
| 41 | /* need enough space in crash buffer to save 8 registers */ |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 42 | #define CPU_DATA_CRASH_BUF_SIZE 64 |
| 43 | #define CPU_DATA_CPU_OPS_PTR 0x10 |
| 44 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 45 | #ifndef __ASSEMBLY__ |
| 46 | |
| 47 | #include <arch_helpers.h> |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 48 | #include <cassert.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 49 | #include <platform_def.h> |
Achin Gupta | f3ccbab | 2014-07-25 14:52:47 +0100 | [diff] [blame] | 50 | #include <psci.h> |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 51 | #include <stdint.h> |
| 52 | |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 53 | /* Offsets for the cpu_data structure */ |
| 54 | #define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\ |
| 55 | (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info) |
| 56 | |
| 57 | #if PLAT_PCPU_DATA_SIZE |
| 58 | #define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\ |
| 59 | (cpu_data_t, platform_cpu_data) |
| 60 | #endif |
| 61 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 62 | /******************************************************************************* |
| 63 | * Function & variable prototypes |
| 64 | ******************************************************************************/ |
| 65 | |
| 66 | /******************************************************************************* |
| 67 | * Cache of frequently used per-cpu data: |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 68 | * Pointers to non-secure and secure security state contexts |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 69 | * Address of the crash stack |
| 70 | * It is aligned to the cache line boundary to allow efficient concurrent |
| 71 | * manipulation of these pointers on different cpus |
| 72 | * |
| 73 | * TODO: Add other commonly used variables to this (tf_issues#90) |
| 74 | * |
| 75 | * The data structure and the _cpu_data accessors should not be used directly |
| 76 | * by components that have per-cpu members. The member access macros should be |
| 77 | * used for this. |
| 78 | ******************************************************************************/ |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 79 | typedef struct cpu_data { |
Andrew Thoelke | c02dbd6 | 2014-06-02 10:00:25 +0100 | [diff] [blame] | 80 | void *cpu_context[2]; |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 81 | uint64_t cpu_ops_ptr; |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 82 | #if CRASH_REPORTING |
| 83 | uint64_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3]; |
| 84 | #endif |
Soby Mathew | 523d633 | 2015-01-08 18:02:19 +0000 | [diff] [blame] | 85 | struct psci_cpu_data psci_svc_cpu_data; |
| 86 | #if PLAT_PCPU_DATA_SIZE |
| 87 | uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE]; |
| 88 | #endif |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 89 | } __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t; |
| 90 | |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 91 | #if CRASH_REPORTING |
| 92 | /* verify assembler offsets match data structures */ |
| 93 | CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof |
| 94 | (cpu_data_t, crash_buf), |
| 95 | assert_cpu_data_crash_stack_offset_mismatch); |
| 96 | #endif |
| 97 | |
| 98 | CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t), |
| 99 | assert_cpu_data_log2size_mismatch); |
| 100 | |
Soby Mathew | c704cbc | 2014-08-14 11:33:56 +0100 | [diff] [blame] | 101 | CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof |
| 102 | (cpu_data_t, cpu_ops_ptr), |
| 103 | assert_cpu_data_cpu_ops_ptr_offset_mismatch); |
| 104 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 105 | struct cpu_data *_cpu_data_by_index(uint32_t cpu_index); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 106 | |
| 107 | /* Return the cpu_data structure for the current CPU. */ |
| 108 | static inline struct cpu_data *_cpu_data(void) |
| 109 | { |
| 110 | return (cpu_data_t *)read_tpidr_el3(); |
| 111 | } |
| 112 | |
| 113 | |
| 114 | /************************************************************************** |
| 115 | * APIs for initialising and accessing per-cpu data |
| 116 | *************************************************************************/ |
| 117 | |
| 118 | void init_cpu_data_ptr(void); |
Vikram Kanigiri | 9b38fc8 | 2015-01-29 18:27:38 +0000 | [diff] [blame] | 119 | void init_cpu_ops(void); |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 120 | |
| 121 | #define get_cpu_data(_m) _cpu_data()->_m |
| 122 | #define set_cpu_data(_m, _v) _cpu_data()->_m = _v |
| 123 | #define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m |
| 124 | #define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 125 | |
Achin Gupta | e4b9fa4 | 2014-07-25 14:47:05 +0100 | [diff] [blame] | 126 | #define flush_cpu_data(_m) flush_dcache_range((uint64_t) \ |
| 127 | &(_cpu_data()->_m), \ |
| 128 | sizeof(_cpu_data()->_m)) |
Soby Mathew | 85dbf5a | 2015-04-07 12:16:56 +0100 | [diff] [blame] | 129 | #define inv_cpu_data(_m) inv_dcache_range((uint64_t) \ |
| 130 | &(_cpu_data()->_m), \ |
| 131 | sizeof(_cpu_data()->_m)) |
Soby Mathew | 7d861ea | 2014-11-18 10:14:14 +0000 | [diff] [blame] | 132 | #define flush_cpu_data_by_index(_ix, _m) \ |
| 133 | flush_dcache_range((uint64_t) \ |
| 134 | &(_cpu_data_by_index(_ix)->_m), \ |
| 135 | sizeof(_cpu_data_by_index(_ix)->_m)) |
Achin Gupta | e4b9fa4 | 2014-07-25 14:47:05 +0100 | [diff] [blame] | 136 | |
Andrew Thoelke | 8c28fe0 | 2014-06-02 11:40:35 +0100 | [diff] [blame] | 137 | |
| 138 | #endif /* __ASSEMBLY__ */ |
| 139 | #endif /* __CPU_DATA_H__ */ |