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Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02001/*
Joel Hutton5cc3bc82018-03-21 11:40:57 +00002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02007#include <assert.h>
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02008#include <errno.h>
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +02009#include <string.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <platform_def.h>
12
13#include <arch_helpers.h>
14#include <common/bl_common.h>
15#include <common/debug.h>
16#include <common/tbbr/tbbr_img_def.h>
17#include <drivers/arm/pl011.h>
18#include <drivers/arm/pl061_gpio.h>
19#include <drivers/generic_delay_timer.h>
20#include <drivers/mmc.h>
21#include <drivers/synopsys/dw_mmc.h>
22#include <lib/mmio.h>
23#include <plat/common/platform.h>
24
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020025#include "hi3798cv200.h"
26#include "plat_private.h"
27
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020028/* Data structure which holds the extents of the trusted RAM for BL1 */
29static meminfo_t bl1_tzram_layout;
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010030static meminfo_t bl2_tzram_layout;
Andre Przywara2b1b1a52020-01-25 00:58:35 +000031static console_t console;
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020032
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010033/*
34 * Cannot use default weak implementation in bl1_main.c because BL1 RW data is
35 * not at the top of the secure memory.
36 */
37int bl1_plat_handle_post_image_load(unsigned int image_id)
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020038{
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010039 image_desc_t *image_desc;
40 entry_point_info_t *ep_info;
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020041
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010042 if (image_id != BL2_IMAGE_ID)
43 return 0;
44
45 /* Get the image descriptor */
46 image_desc = bl1_plat_get_image_desc(BL2_IMAGE_ID);
47 assert(image_desc != NULL);
48
49 /* Get the entry point info */
50 ep_info = &image_desc->ep_info;
Victor Chong175dd8a2018-02-01 00:35:22 +090051
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010052 bl2_tzram_layout.total_base = BL2_BASE;
53 bl2_tzram_layout.total_size = BL32_LIMIT - BL2_BASE;
Victor Chong175dd8a2018-02-01 00:35:22 +090054
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010055 flush_dcache_range((uintptr_t)&bl2_tzram_layout, sizeof(meminfo_t));
Victor Chong175dd8a2018-02-01 00:35:22 +090056
Antonio Nino Diaze93cde12018-09-24 17:15:15 +010057 ep_info->args.arg1 = (uintptr_t)&bl2_tzram_layout;
58
59 VERBOSE("BL1: BL2 memory layout address = %p\n",
60 (void *)&bl2_tzram_layout);
61
62 return 0;
Victor Chong175dd8a2018-02-01 00:35:22 +090063}
Victor Chong175dd8a2018-02-01 00:35:22 +090064
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020065void bl1_early_platform_setup(void)
66{
67 /* Initialize the console to provide early debug support */
Jerome Forissier74a19f22018-11-08 11:57:30 +000068 console_pl011_register(PL011_UART0_BASE, PL011_UART0_CLK_IN_HZ,
69 PL011_BAUDRATE, &console);
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020070
71 /* Allow BL1 to see the whole Trusted RAM */
Victor Chong175dd8a2018-02-01 00:35:22 +090072 bl1_tzram_layout.total_base = BL1_RW_BASE;
73 bl1_tzram_layout.total_size = BL1_RW_SIZE;
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020074
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020075 INFO("BL1: 0x%lx - 0x%lx [size = %zu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
76 BL1_RAM_LIMIT - BL1_RAM_BASE);
77}
78
79void bl1_plat_arch_setup(void)
80{
81 plat_configure_mmu_el3(bl1_tzram_layout.total_base,
82 bl1_tzram_layout.total_size,
Victor Chong175dd8a2018-02-01 00:35:22 +090083 BL1_RO_BASE, /* l-loader and BL1 ROM */
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020084 BL1_RO_LIMIT,
Joel Hutton5cc3bc82018-03-21 11:40:57 +000085 BL_COHERENT_RAM_BASE,
86 BL_COHERENT_RAM_END);
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020087}
88
89void bl1_platform_setup(void)
90{
91 int i;
Victor Chongf0c7c612018-01-16 00:29:47 +090092#if !POPLAR_RECOVERY
Shawn Guod793ff02018-09-27 16:48:00 +080093 struct mmc_device_info info;
Victor Chong539408d2018-01-03 01:53:08 +090094 dw_mmc_params_t params = EMMC_INIT_PARAMS(POPLAR_EMMC_DESC_BASE);
Victor Chongf0c7c612018-01-16 00:29:47 +090095#endif
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +020096
97 generic_delay_timer_init();
98
99 pl061_gpio_init();
100 for (i = 0; i < GPIO_MAX; i++)
101 pl061_gpio_register(GPIO_BASE(i), i);
102
Victor Chongf0c7c612018-01-16 00:29:47 +0900103#if !POPLAR_RECOVERY
Victor Chong539408d2018-01-03 01:53:08 +0900104 /* SoC-specific emmc register are initialized/configured by bootrom */
105 INFO("BL1: initializing emmc\n");
Haojian Zhuang3eff4092018-08-04 18:07:26 +0800106 info.mmc_dev_type = MMC_IS_EMMC;
107 dw_mmc_init(&params, &info);
Victor Chongf0c7c612018-01-16 00:29:47 +0900108#endif
Victor Chong539408d2018-01-03 01:53:08 +0900109
Jorge Ramirez-Ortiza29d9a62017-06-28 10:11:31 +0200110 plat_io_setup();
111}
112
113unsigned int bl1_plat_get_next_image_id(void)
114{
115 return BL2_IMAGE_ID;
116}