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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Antonio Nino Diaz25cda672019-02-19 11:53:51 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef BL_COMMON_H
8#define BL_COMMON_H
Achin Gupta4f6ad662013-10-25 09:08:21 +01009
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/ep_info.h>
11#include <common/param_header.h>
12#include <lib/utils_def.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010013
Julius Werner2a231e32019-05-28 21:03:58 -070014#ifndef __ASSEMBLY__
15#include <stddef.h>
16#include <stdint.h>
17#include <lib/cassert.h>
18#endif /* __ASSEMBLY__ */
19
20#include <export/common/bl_common_exp.h>
21
Antonio Nino Diazf0b14cf2018-10-04 09:55:23 +010022#define UP U(1)
23#define DOWN U(0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010024
25/*******************************************************************************
Sandrine Bailleux467d0572014-06-24 14:02:34 +010026 * Constants to identify the location of a memory region in a given memory
27 * layout.
28******************************************************************************/
Antonio Nino Diazf0b14cf2018-10-04 09:55:23 +010029#define TOP U(0x1)
30#define BOTTOM U(0x0)
Achin Gupta4f6ad662013-10-25 09:08:21 +010031
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010032/*******************************************************************************
33 * Constants to indicate type of exception to the common exception handler.
34 ******************************************************************************/
Antonio Nino Diazf0b14cf2018-10-04 09:55:23 +010035#define SYNC_EXCEPTION_SP_EL0 U(0x0)
36#define IRQ_SP_EL0 U(0x1)
37#define FIQ_SP_EL0 U(0x2)
38#define SERROR_SP_EL0 U(0x3)
39#define SYNC_EXCEPTION_SP_ELX U(0x4)
40#define IRQ_SP_ELX U(0x5)
41#define FIQ_SP_ELX U(0x6)
42#define SERROR_SP_ELX U(0x7)
43#define SYNC_EXCEPTION_AARCH64 U(0x8)
44#define IRQ_AARCH64 U(0x9)
45#define FIQ_AARCH64 U(0xa)
46#define SERROR_AARCH64 U(0xb)
47#define SYNC_EXCEPTION_AARCH32 U(0xc)
48#define IRQ_AARCH32 U(0xd)
49#define FIQ_AARCH32 U(0xe)
50#define SERROR_AARCH32 U(0xf)
Yatharth Kochar6c0566c2015-10-02 17:56:48 +010051
Varun Wadekar4d034c52019-01-11 14:47:48 -080052/*
53 * Mapping to connect linker symbols from .ld.S with their counterparts
54 * from .scat for the BL31 image
55 */
56#if defined(USE_ARM_LINK)
57#define __BL31_END__ Load$$LR$$LR_END$$Base
58#define __BSS_START__ Load$$LR$$LR_BSS$$Base
59#define __BSS_END__ Load$$LR$$LR_BSS$$Limit
60#define __BSS_SIZE__ Load$$LR$$LR_BSS$$Length
61#define __COHERENT_RAM_START__ Load$$LR$$LR_COHERENT_RAM$$Base
62#define __COHERENT_RAM_END_UNALIGNED__ Load$$__COHERENT_RAM_EPILOGUE_UNALIGNED__$$Base
63#define __COHERENT_RAM_END__ Load$$LR$$LR_COHERENT_RAM$$Limit
64#define __COHERENT_RAM_UNALIGNED_SIZE__ Load$$__COHERENT_RAM__$$Length
65#define __CPU_OPS_START__ Load$$__CPU_OPS__$$Base
66#define __CPU_OPS_END__ Load$$__CPU_OPS__$$Limit
67#define __DATA_START__ Load$$__DATA__$$Base
68#define __DATA_END__ Load$$__DATA__$$Limit
69#define __GOT_START__ Load$$__GOT__$$Base
70#define __GOT_END__ Load$$__GOT__$$Limit
71#define __PERCPU_BAKERY_LOCK_START__ Load$$__BAKERY_LOCKS__$$Base
72#define __PERCPU_BAKERY_LOCK_END__ Load$$__BAKERY_LOCKS_EPILOGUE__$$Base
73#define __PMF_SVC_DESCS_START__ Load$$__PMF_SVC_DESCS__$$Base
74#define __PMF_SVC_DESCS_END__ Load$$__PMF_SVC_DESCS__$$Limit
75#define __PMF_TIMESTAMP_START__ Load$$__PMF_TIMESTAMP__$$Base
76#define __PMF_TIMESTAMP_END__ Load$$__PER_CPU_TIMESTAMPS__$$Limit
77#define __PMF_PERCPU_TIMESTAMP_END__ Load$$__PMF_TIMESTAMP_EPILOGUE__$$Base
78#define __RELA_END__ Load$$__RELA__$$Limit
79#define __RELA_START__ Load$$__RELA__$$Base
80#define __RODATA_START__ Load$$__RODATA__$$Base
81#define __RODATA_END__ Load$$__RODATA_EPILOGUE__$$Base
82#define __RT_SVC_DESCS_START__ Load$$__RT_SVC_DESCS__$$Base
83#define __RT_SVC_DESCS_END__ Load$$__RT_SVC_DESCS__$$Limit
84#define __RW_START__ Load$$LR$$LR_RW_DATA$$Base
85#define __RW_END__ Load$$LR$$LR_END$$Base
86#define __SPM_SHIM_EXCEPTIONS_START__ Load$$__SPM_SHIM_EXCEPTIONS__$$Base
87#define __SPM_SHIM_EXCEPTIONS_END__ Load$$__SPM_SHIM_EXCEPTIONS_EPILOGUE__$$Base
88#define __STACKS_START__ Load$$__STACKS__$$Base
89#define __STACKS_END__ Load$$__STACKS__$$Limit
90#define __TEXT_START__ Load$$__TEXT__$$Base
91#define __TEXT_END__ Load$$__TEXT_EPILOGUE__$$Base
92#endif /* USE_ARM_LINK */
93
Vikram Kanigirida567432014-04-15 18:08:08 +010094#ifndef __ASSEMBLY__
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000095
Dan Handleyf05c1b52015-04-27 11:49:22 +010096/*
97 * Declarations of linker defined symbols to help determine memory layout of
98 * BL images
99 */
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100100#if SEPARATE_CODE_AND_RODATA
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000101IMPORT_SYM(uintptr_t, __TEXT_START__, BL_CODE_BASE);
102IMPORT_SYM(uintptr_t, __TEXT_END__, BL_CODE_END);
103IMPORT_SYM(uintptr_t, __RODATA_START__, BL_RO_DATA_BASE);
104IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100105#else
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000106IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
107IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100108#endif
109
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000110#if defined(IMAGE_BL1)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000111IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000112
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000113IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
114IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000115#elif defined(IMAGE_BL2)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000116IMPORT_SYM(uintptr_t, __BL2_END__, BL2_END);
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900117#elif defined(IMAGE_BL2U)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000118IMPORT_SYM(uintptr_t, __BL2U_END__, BL2U_END);
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900119#elif defined(IMAGE_BL31)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000120IMPORT_SYM(uintptr_t, __BL31_START__, BL31_START);
121IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END);
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900122#elif defined(IMAGE_BL32)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000123IMPORT_SYM(uintptr_t, __BL32_END__, BL32_END);
Dan Handleyf05c1b52015-04-27 11:49:22 +0100124#endif /* IMAGE_BLX */
125
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000126/* The following symbols are only exported from the BL2 at EL3 linker script. */
127#if BL2_IN_XIP_MEM && defined(IMAGE_BL2)
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000128IMPORT_SYM(uintptr_t, __BL2_ROM_END__, BL2_ROM_END);
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000129
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000130IMPORT_SYM(uintptr_t, __BL2_RAM_START__, BL2_RAM_BASE);
131IMPORT_SYM(uintptr_t, __BL2_RAM_END__, BL2_RAM_END);
Antonio Nino Diazb0fd0082018-12-18 13:49:46 +0000132#endif /* BL2_IN_XIP_MEM */
133
Joel Hutton5cc3bc82018-03-21 11:40:57 +0000134/*
135 * The next 2 constants identify the extents of the coherent memory region.
136 * These addresses are used by the MMU setup code and therefore they must be
137 * page-aligned. It is the responsibility of the linker script to ensure that
138 * __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
139 * page-aligned addresses.
140 */
Dan Handleyf05c1b52015-04-27 11:49:22 +0100141#if USE_COHERENT_MEM
Antonio Nino Diazde97ff32019-01-25 13:28:38 +0000142IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
143IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
Dan Handleyf05c1b52015-04-27 11:49:22 +0100144#endif
145
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146/*******************************************************************************
147 * Structure used for telling the next BL how much of a particular type of
148 * memory is available for its use and how much is already used.
149 ******************************************************************************/
Dan Handleye2712bc2014-04-10 15:37:22 +0100150typedef struct meminfo {
Soby Mathewa0fedc42016-06-16 14:52:04 +0100151 uintptr_t total_base;
Sandrine Bailleux467d0572014-06-24 14:02:34 +0100152 size_t total_size;
Dan Handleye2712bc2014-04-10 15:37:22 +0100153} meminfo_t;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100154
Achin Guptae4d084e2014-02-19 17:18:23 +0000155/*******************************************************************************
Achin Gupta4f6ad662013-10-25 09:08:21 +0100156 * Function & variable prototypes
157 ******************************************************************************/
Yatharth Kochar3345a8d2016-09-12 16:08:41 +0100158int load_auth_image(unsigned int image_id, image_info_t *image_data);
159
Soby Mathew9fe88042018-03-26 12:43:37 +0100160#if TRUSTED_BOARD_BOOT && defined(DYN_DISABLE_AUTH)
161/*
162 * API to dynamically disable authentication. Only meant for development
163 * systems.
164 */
165void dyn_disable_auth(void);
166#endif
167
Yatharth Kochar3345a8d2016-09-12 16:08:41 +0100168extern const char build_message[];
169extern const char version_string[];
170
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +0100171void print_entry_point_info(const entry_point_info_t *ep_info);
Roberto Vargas2ca18d92018-02-12 12:36:17 +0000172uintptr_t page_align(uintptr_t value, unsigned dir);
Sandrine Bailleuxb2e224c2015-09-28 17:03:06 +0100173
Roberto Vargas344ff022018-10-19 16:44:18 +0100174struct mmap_region;
175
176void setup_page_tables(const struct mmap_region *bl_regions,
177 const struct mmap_region *plat_regions);
178
Antonio Nino Diaz25cda672019-02-19 11:53:51 +0000179void bl_handle_pauth(void);
180
Achin Gupta4f6ad662013-10-25 09:08:21 +0100181#endif /*__ASSEMBLY__*/
182
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000183#endif /* BL_COMMON_H */