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git01.mediatek.com / filogic / atf / 693873157cf5ac8d80b91d72f991910950824f08 / . / plat / nvidia / tegra / include / platform_def.h
blob: 41d771c037da7c29e8e388b5825c9977b5925d70 [file] [log] [blame]
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]1/*
Varun Wadekarb5132322017-04-10 15:30:17 -0700[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include <common_def.h>
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]12#include <tegra_def.h>
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]13
14/*******************************************************************************
15 * Generic platform constants
16 ******************************************************************************/
17
18/* Size of cacheable stacks */
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900[diff] [blame]19#ifdef IMAGE_BL31
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]20#define PLATFORM_STACK_SIZE 0x400
21#endif
22
23#define TEGRA_PRIMARY_CPU 0x0
24
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]25#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]26#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
27 PLATFORM_MAX_CPUS_PER_CLUSTER)
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]28#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
Varun Wadekar88c4d222015-08-12 09:24:50 +0530[diff] [blame]29 PLATFORM_CLUSTER_COUNT + 1)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]30
31/*******************************************************************************
32 * Platform console related constants
33 ******************************************************************************/
34#define TEGRA_CONSOLE_BAUDRATE 115200
35#define TEGRA_BOOT_UART_CLK_IN_HZ 408000000
36
37/*******************************************************************************
38 * Platform memory map related constants
39 ******************************************************************************/
40/* Size of trusted dram */
41#define TZDRAM_SIZE 0x00400000
42#define TZDRAM_END (TZDRAM_BASE + TZDRAM_SIZE)
43
44/*******************************************************************************
45 * BL31 specific defines.
46 ******************************************************************************/
Varun Wadekare0323632016-03-03 18:27:28 -0800[diff] [blame]47#define BL31_SIZE 0x40000
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]48#define BL31_BASE TZDRAM_BASE
Varun Wadekar52a15982015-06-05 12:57:27 +0530[diff] [blame]49#define BL31_LIMIT (TZDRAM_BASE + BL31_SIZE - 1)
50#define BL32_BASE (TZDRAM_BASE + BL31_SIZE)
51#define BL32_LIMIT TZDRAM_END
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]52
53/*******************************************************************************
54 * Platform specific page table and MMU setup constants
55 ******************************************************************************/
Varun Wadekarb5132322017-04-10 15:30:17 -0700[diff] [blame]56#define PLAT_PHY_ADDR_SPACE_SIZE (1ull << 35)
57#define PLAT_VIRT_ADDR_SPACE_SIZE (1ull << 35)
Varun Wadekarb316e242015-05-19 16:48:04 +0530[diff] [blame]58
59/*******************************************************************************
60 * Some data must be aligned on the biggest cache line size in the platform.
61 * This is known only to the platform as it might have a combination of
62 * integrated and external caches.
63 ******************************************************************************/
64#define CACHE_WRITEBACK_SHIFT 6
65#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
66
67#endif /* __PLATFORM_DEF_H__ */