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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Achin Gupta69387312016-09-26 10:22:56 +01002 * Copyright (c) 2013-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
Achin Gupta69387312016-09-26 10:22:56 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
7/dts-v1/;
8
9/memreserve/ 0x80000000 0x00010000;
10
11/ {
12};
13
14/ {
15 model = "FVP Base";
16 compatible = "arm,vfp-base", "arm,vexpress";
17 interrupt-parent = <&gic>;
18 #address-cells = <2>;
19 #size-cells = <2>;
20
21 chosen { };
22
23 aliases {
24 serial0 = &v2m_serial0;
25 serial1 = &v2m_serial1;
26 serial2 = &v2m_serial2;
27 serial3 = &v2m_serial3;
28 };
29
30 psci {
Soby Mathew1df077b2015-01-15 11:49:58 +000031 compatible = "arm,psci-1.0", "arm,psci-0.2", "arm,psci";
Achin Gupta4f6ad662013-10-25 09:08:21 +010032 method = "smc";
33 cpu_suspend = <0xc4000001>;
34 cpu_off = <0x84000002>;
35 cpu_on = <0xc4000003>;
Soby Mathewe0f55df2016-10-05 15:38:01 +010036 sys_poweroff = <0x84000008>;
37 sys_reset = <0x84000009>;
Achin Gupta4f6ad662013-10-25 09:08:21 +010038 };
39
40 cpus {
41 #address-cells = <2>;
42 #size-cells = <0>;
43
Achin Gupta5ab4fe42014-08-20 17:33:09 +010044 cpu-map {
45 cluster0 {
46 core0 {
47 cpu = <&CPU0>;
48 };
49 core1 {
50 cpu = <&CPU1>;
51 };
52 core2 {
53 cpu = <&CPU2>;
54 };
55 core3 {
56 cpu = <&CPU3>;
57 };
58 };
59
60 cluster1 {
61 core0 {
62 cpu = <&CPU4>;
63 };
64 core1 {
65 cpu = <&CPU5>;
66 };
67 core2 {
68 cpu = <&CPU6>;
69 };
70 core3 {
71 cpu = <&CPU7>;
72 };
73 };
74 };
75
76 idle-states {
77 entry-method = "arm,psci";
78
79 CPU_SLEEP_0: cpu-sleep-0 {
80 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010081 local-timer-stop;
82 arm,psci-suspend-param = <0x0010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010083 entry-latency-us = <40>;
84 exit-latency-us = <100>;
85 min-residency-us = <150>;
86 };
87
88 CLUSTER_SLEEP_0: cluster-sleep-0 {
89 compatible = "arm,idle-state";
Juan Castillo3414f542015-04-16 14:17:49 +010090 local-timer-stop;
91 arm,psci-suspend-param = <0x1010000>;
Achin Gupta5ab4fe42014-08-20 17:33:09 +010092 entry-latency-us = <500>;
93 exit-latency-us = <1000>;
94 min-residency-us = <2500>;
95 };
96 };
97
98 CPU0:cpu@0 {
Achin Gupta4f6ad662013-10-25 09:08:21 +010099 device_type = "cpu";
100 compatible = "arm,armv8";
101 reg = <0x0 0x0>;
102 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100103 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000104 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100105 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100106
107 CPU1:cpu@1 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100108 device_type = "cpu";
109 compatible = "arm,armv8";
110 reg = <0x0 0x1>;
111 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100112 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000113 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100114 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100115
116 CPU2:cpu@2 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100117 device_type = "cpu";
118 compatible = "arm,armv8";
119 reg = <0x0 0x2>;
120 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100121 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000122 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100124
125 CPU3:cpu@3 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100126 device_type = "cpu";
127 compatible = "arm,armv8";
128 reg = <0x0 0x3>;
129 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100130 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000131 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100132 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100133
134 CPU4:cpu@100 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100135 device_type = "cpu";
136 compatible = "arm,armv8";
137 reg = <0x0 0x100>;
138 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100139 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000140 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100141 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100142
143 CPU5:cpu@101 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144 device_type = "cpu";
145 compatible = "arm,armv8";
146 reg = <0x0 0x101>;
147 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100148 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000149 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100150 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100151
152 CPU6:cpu@102 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100153 device_type = "cpu";
154 compatible = "arm,armv8";
155 reg = <0x0 0x102>;
156 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100157 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000158 next-level-cache = <&L2_0>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100159 };
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100160
161 CPU7:cpu@103 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162 device_type = "cpu";
163 compatible = "arm,armv8";
164 reg = <0x0 0x103>;
165 enable-method = "psci";
Achin Gupta5ab4fe42014-08-20 17:33:09 +0100166 cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
Antonio Nino Diaz430147a2016-02-22 16:44:41 +0000167 next-level-cache = <&L2_0>;
168 };
169
170 L2_0: l2-cache0 {
171 compatible = "cache";
Achin Gupta4f6ad662013-10-25 09:08:21 +0100172 };
173 };
174
175 memory@80000000 {
176 device_type = "memory";
Juan Castillo7055ca42014-05-16 15:33:15 +0100177 reg = <0x00000000 0x80000000 0 0x7F000000>,
Achin Gupta4f6ad662013-10-25 09:08:21 +0100178 <0x00000008 0x80000000 0 0x80000000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100179 };
180
Harry Liebel34988592013-11-11 13:24:47 +0000181 gic: interrupt-controller@2f000000 {
Achin Gupta4f6ad662013-10-25 09:08:21 +0100182 compatible = "arm,gic-v3";
183 #interrupt-cells = <3>;
Harry Liebel34988592013-11-11 13:24:47 +0000184 #address-cells = <2>;
185 #size-cells = <2>;
186 ranges;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100187 interrupt-controller;
188 reg = <0x0 0x2f000000 0 0x10000>, // GICD
189 <0x0 0x2f100000 0 0x200000>, // GICR
190 <0x0 0x2c000000 0 0x2000>, // GICC
191 <0x0 0x2c010000 0 0x2000>, // GICH
Harry Liebel34988592013-11-11 13:24:47 +0000192 <0x0 0x2c02f000 0 0x2000>; // GICV
Achin Gupta4f6ad662013-10-25 09:08:21 +0100193 interrupts = <1 9 4>;
Harry Liebel34988592013-11-11 13:24:47 +0000194
195 its: its@2f020000 {
196 compatible = "arm,gic-v3-its";
197 msi-controller;
198 reg = <0x0 0x2f020000 0x0 0x20000>; // GITS
199 };
Achin Gupta4f6ad662013-10-25 09:08:21 +0100200 };
201
202 timer {
203 compatible = "arm,armv8-timer";
204 interrupts = <1 13 0xff01>,
205 <1 14 0xff01>,
206 <1 11 0xff01>,
207 <1 10 0xff01>;
208 clock-frequency = <100000000>;
209 };
210
211 timer@2a810000 {
212 compatible = "arm,armv7-timer-mem";
213 reg = <0x0 0x2a810000 0x0 0x10000>;
214 clock-frequency = <100000000>;
215 #address-cells = <2>;
216 #size-cells = <2>;
217 ranges;
Harry Liebelcef93392014-04-01 19:27:38 +0100218 frame@2a830000 {
219 frame-number = <1>;
220 interrupts = <0 26 4>;
221 reg = <0x0 0x2a830000 0x0 0x10000>;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100222 };
223 };
224
225 pmu {
226 compatible = "arm,armv8-pmuv3";
227 interrupts = <0 60 4>,
228 <0 61 4>,
229 <0 62 4>,
230 <0 63 4>;
231 };
232
233 smb {
234 compatible = "simple-bus";
235
236 #address-cells = <2>;
237 #size-cells = <1>;
238 ranges = <0 0 0 0x08000000 0x04000000>,
239 <1 0 0 0x14000000 0x04000000>,
240 <2 0 0 0x18000000 0x04000000>,
241 <3 0 0 0x1c000000 0x04000000>,
242 <4 0 0 0x0c000000 0x04000000>,
243 <5 0 0 0x10000000 0x04000000>;
244
Soby Mathewe0f55df2016-10-05 15:38:01 +0100245 /include/ "rtsm_ve-motherboard.dtsi"
Achin Gupta4f6ad662013-10-25 09:08:21 +0100246 };
247
248 panels {
249 panel@0 {
250 compatible = "panel";
251 mode = "XVGA";
252 refresh = <60>;
253 xres = <1024>;
254 yres = <768>;
255 pixclock = <15748>;
256 left_margin = <152>;
257 right_margin = <48>;
258 upper_margin = <23>;
259 lower_margin = <3>;
260 hsync_len = <104>;
261 vsync_len = <4>;
262 sync = <0>;
263 vmode = "FB_VMODE_NONINTERLACED";
264 tim2 = "TIM2_BCD", "TIM2_IPC";
265 cntl = "CNTL_LCDTFT", "CNTL_BGR", "CNTL_LCDVCOMP(1)";
266 caps = "CLCD_CAP_5551", "CLCD_CAP_565", "CLCD_CAP_888";
267 bpp = <16>;
268 };
269 };
270};