blob: cb7609076cda342dffe3c56f75b65a06038398cf [file] [log] [blame]
Haojian Zhuang602362d2017-06-01 12:15:14 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __PLATFORM_DEF_H__
8#define __PLATFORM_DEF_H__
9
10#include <arch.h>
11#include "../hikey960_def.h"
12
Victor Chong2d9a42d2017-08-17 15:21:10 +090013/* Special value used to verify platform parameters from BL2 to BL3-1 */
14#define HIKEY960_BL31_PLAT_PARAM_VAL 0x0f1e2d3c4b5a6978ULL
Haojian Zhuang602362d2017-06-01 12:15:14 +080015
16/*
17 * Generic platform constants
18 */
19
20/* Size of cacheable stacks */
21#define PLATFORM_STACK_SIZE 0x800
22
23#define FIRMWARE_WELCOME_STR "Booting Trusted Firmware\n"
24
25#define PLATFORM_CACHE_LINE_SIZE 64
26#define PLATFORM_CLUSTER_COUNT 2
27#define PLATFORM_CORE_COUNT_PER_CLUSTER 4
28#define PLATFORM_CORE_COUNT (PLATFORM_CLUSTER_COUNT * \
29 PLATFORM_CORE_COUNT_PER_CLUSTER)
30#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL2
31#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
32 PLATFORM_CLUSTER_COUNT + 1)
33
Leo Yan6829b702018-01-03 14:52:19 +080034#define PLAT_MAX_RET_STATE 1
35#define PLAT_MAX_OFF_STATE 2
Haojian Zhuang602362d2017-06-01 12:15:14 +080036
37#define MAX_IO_DEVICES 3
38#define MAX_IO_HANDLES 4
39/* UFS RPMB and UFS User Data */
40#define MAX_IO_BLOCK_DEVICES 2
41
42
43/*
44 * Platform memory map related constants
45 */
46
47/*
48 * BL1 specific defines.
49 */
50#define BL1_RO_BASE (0x1AC00000)
51#define BL1_RO_LIMIT (BL1_RO_BASE + 0x10000)
52#define BL1_RW_BASE (BL1_RO_LIMIT) /* 1AC1_0000 */
53#define BL1_RW_SIZE (0x00188000)
54#define BL1_RW_LIMIT (0x1B000000)
55
56/*
57 * BL2 specific defines.
58 */
59#define BL2_BASE (BL1_RW_BASE + 0x8000) /* 1AC1_8000 */
60#define BL2_LIMIT (BL2_BASE + 0x40000) /* 1AC5_8000 */
61
62/*
63 * BL31 specific defines.
64 */
65#define BL31_BASE (BL2_LIMIT) /* 1AC5_8000 */
66#define BL31_LIMIT (BL31_BASE + 0x40000) /* 1AC9_8000 */
67
Victor Chong91287682017-05-28 00:14:37 +090068/*
69 * BL3-2 specific defines.
70 */
71
72/*
73 * The TSP currently executes from TZC secured area of DRAM.
74 */
75#define BL32_DRAM_BASE DDR_SEC_BASE
76#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
77
Victor Chong7d787f52017-08-16 13:53:56 +090078#if LOAD_IMAGE_V2
79#ifdef SPD_opteed
80/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
81#define HIKEY960_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
82#define HIKEY960_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
83#endif
84#endif
85
Victor Chong91287682017-05-28 00:14:37 +090086#if (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_DRAM_ID)
87#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
88#define TSP_SEC_MEM_SIZE (BL32_DRAM_LIMIT - BL32_DRAM_BASE)
89#define BL32_BASE BL32_DRAM_BASE
90#define BL32_LIMIT BL32_DRAM_LIMIT
91#elif (HIKEY960_TSP_RAM_LOCATION_ID == HIKEY960_SRAM_ID)
92#error "SRAM storage of TSP payload is currently unsupported"
93#else
94#error "Currently unsupported HIKEY960_TSP_LOCATION_ID value"
95#endif
96
Victor Chong398d5d32017-09-14 01:27:19 +090097/* BL32 is mandatory in AArch32 */
98#ifndef AARCH32
99#ifdef SPD_none
100#undef BL32_BASE
101#endif /* SPD_none */
102#endif
103
Haojian Zhuang602362d2017-06-01 12:15:14 +0800104#define NS_BL1U_BASE (BL31_LIMIT) /* 1AC9_8000 */
105#define NS_BL1U_SIZE (0x00100000)
106#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
107
108#define HIKEY960_NS_IMAGE_OFFSET (0x1AC18000) /* offset in l-loader */
109#define HIKEY960_NS_TMP_OFFSET (0x1AE00000)
110
Victor Chong2d9a42d2017-08-17 15:21:10 +0900111#define SCP_BL2_BASE (0x89C80000)
112#define SCP_BL2_SIZE (0x00040000)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800113
114/*
115 * Platform specific page table and MMU setup constants
116 */
117#define ADDR_SPACE_SIZE (1ull << 32)
118
Roberto Vargas82477962017-10-23 08:22:17 +0100119#if defined(IMAGE_BL1) || defined(IMAGE_BL31) || defined(IMAGE_BL32)
Haojian Zhuang602362d2017-06-01 12:15:14 +0800120#define MAX_XLAT_TABLES 3
121#endif
122
Roberto Vargas82477962017-10-23 08:22:17 +0100123#ifdef IMAGE_BL2
Victor Chong7d787f52017-08-16 13:53:56 +0900124#if LOAD_IMAGE_V2
125#ifdef SPD_opteed
126#define MAX_XLAT_TABLES 4
127#else
128#define MAX_XLAT_TABLES 3
129#endif
130#else
131#define MAX_XLAT_TABLES 3
132#endif
133#endif
134
Haojian Zhuang602362d2017-06-01 12:15:14 +0800135#define MAX_MMAP_REGIONS 16
136
137/*
138 * Declarations and constants to access the mailboxes safely. Each mailbox is
139 * aligned on the biggest cache line size in the platform. This is known only
140 * to the platform as it might have a combination of integrated and external
141 * caches. Such alignment ensures that two maiboxes do not sit on the same cache
142 * line at any cache level. They could belong to different cpus/clusters &
143 * get written while being protected by different locks causing corruption of
144 * a valid mailbox address.
145 */
146#define CACHE_WRITEBACK_SHIFT 6
147#define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT)
148
149#endif /* __PLATFORM_DEF_H__ */