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Andrew Thoelke8c28fe02014-06-02 11:40:35 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01005 */
6
7#ifndef __CPU_DATA_H__
8#define __CPU_DATA_H__
9
Soby Mathew748be1d2016-05-05 14:10:46 +010010#ifdef AARCH32
11
12#if CRASH_REPORTING
13#error "Crash reporting is not supported in AArch32"
14#endif
15#define CPU_DATA_CPU_OPS_PTR 0x0
16
17#else /* AARCH32 */
18
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010019/* Offsets for the cpu_data structure */
Soby Mathew523d6332015-01-08 18:02:19 +000020#define CPU_DATA_CRASH_BUF_OFFSET 0x18
Soby Mathew748be1d2016-05-05 14:10:46 +010021/* need enough space in crash buffer to save 8 registers */
22#define CPU_DATA_CRASH_BUF_SIZE 64
23#define CPU_DATA_CPU_OPS_PTR 0x10
24
25#endif /* AARCH32 */
26
Soby Mathewc1adbbc2014-06-25 10:07:40 +010027#if CRASH_REPORTING
28#define CPU_DATA_LOG2SIZE 7
dp-arm3cac7862016-09-19 11:18:44 +010029#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
30 CPU_DATA_CRASH_BUF_SIZE)
Soby Mathewc1adbbc2014-06-25 10:07:40 +010031#else
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010032#define CPU_DATA_LOG2SIZE 6
dp-arm3cac7862016-09-19 11:18:44 +010033#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
Soby Mathewc1adbbc2014-06-25 10:07:40 +010034#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010035
dp-arm3cac7862016-09-19 11:18:44 +010036#if ENABLE_RUNTIME_INSTRUMENTATION
37/* Temporary space to store PMF timestamps from assembly code */
38#define CPU_DATA_PMF_TS_COUNT 1
39#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
40#define CPU_DATA_PMF_TS0_IDX 0
41#endif
42
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010043#ifndef __ASSEMBLY__
44
45#include <arch_helpers.h>
Soby Mathew523d6332015-01-08 18:02:19 +000046#include <cassert.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010047#include <platform_def.h>
Achin Guptaf3ccbab2014-07-25 14:52:47 +010048#include <psci.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010049#include <stdint.h>
50
Soby Mathew523d6332015-01-08 18:02:19 +000051/* Offsets for the cpu_data structure */
52#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
53 (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
54
55#if PLAT_PCPU_DATA_SIZE
56#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
57 (cpu_data_t, platform_cpu_data)
58#endif
59
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010060/*******************************************************************************
61 * Function & variable prototypes
62 ******************************************************************************/
63
64/*******************************************************************************
65 * Cache of frequently used per-cpu data:
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010066 * Pointers to non-secure and secure security state contexts
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010067 * Address of the crash stack
68 * It is aligned to the cache line boundary to allow efficient concurrent
69 * manipulation of these pointers on different cpus
70 *
71 * TODO: Add other commonly used variables to this (tf_issues#90)
72 *
73 * The data structure and the _cpu_data accessors should not be used directly
74 * by components that have per-cpu members. The member access macros should be
75 * used for this.
76 ******************************************************************************/
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010077typedef struct cpu_data {
Soby Mathew748be1d2016-05-05 14:10:46 +010078#ifndef AARCH32
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010079 void *cpu_context[2];
Soby Mathew748be1d2016-05-05 14:10:46 +010080#endif
Soby Mathewa0fedc42016-06-16 14:52:04 +010081 uintptr_t cpu_ops_ptr;
Soby Mathewc1adbbc2014-06-25 10:07:40 +010082#if CRASH_REPORTING
Soby Mathewa0fedc42016-06-16 14:52:04 +010083 u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
Soby Mathewc1adbbc2014-06-25 10:07:40 +010084#endif
dp-arm3cac7862016-09-19 11:18:44 +010085#if ENABLE_RUNTIME_INSTRUMENTATION
86 uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
87#endif
Soby Mathew523d6332015-01-08 18:02:19 +000088 struct psci_cpu_data psci_svc_cpu_data;
89#if PLAT_PCPU_DATA_SIZE
90 uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
91#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010092} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
93
Soby Mathewc1adbbc2014-06-25 10:07:40 +010094#if CRASH_REPORTING
95/* verify assembler offsets match data structures */
96CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
97 (cpu_data_t, crash_buf),
98 assert_cpu_data_crash_stack_offset_mismatch);
99#endif
100
101CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t),
102 assert_cpu_data_log2size_mismatch);
103
Soby Mathewc704cbc2014-08-14 11:33:56 +0100104CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
105 (cpu_data_t, cpu_ops_ptr),
106 assert_cpu_data_cpu_ops_ptr_offset_mismatch);
107
dp-arm3cac7862016-09-19 11:18:44 +0100108#if ENABLE_RUNTIME_INSTRUMENTATION
109CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
110 (cpu_data_t, cpu_data_pmf_ts[0]),
111 assert_cpu_data_pmf_ts0_offset_mismatch);
112#endif
113
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100114struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100115
Soby Mathew748be1d2016-05-05 14:10:46 +0100116#ifndef AARCH32
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100117/* Return the cpu_data structure for the current CPU. */
118static inline struct cpu_data *_cpu_data(void)
119{
120 return (cpu_data_t *)read_tpidr_el3();
121}
Soby Mathew748be1d2016-05-05 14:10:46 +0100122#else
123struct cpu_data *_cpu_data(void);
124#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100125
126/**************************************************************************
127 * APIs for initialising and accessing per-cpu data
128 *************************************************************************/
129
130void init_cpu_data_ptr(void);
Vikram Kanigiri9b38fc82015-01-29 18:27:38 +0000131void init_cpu_ops(void);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100132
133#define get_cpu_data(_m) _cpu_data()->_m
134#define set_cpu_data(_m, _v) _cpu_data()->_m = _v
135#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
136#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100137
Soby Mathew24ab34f2016-05-03 17:11:42 +0100138#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
Achin Guptae4b9fa42014-07-25 14:47:05 +0100139 &(_cpu_data()->_m), \
140 sizeof(_cpu_data()->_m))
Soby Mathew24ab34f2016-05-03 17:11:42 +0100141#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100142 &(_cpu_data()->_m), \
143 sizeof(_cpu_data()->_m))
Soby Mathew7d861ea2014-11-18 10:14:14 +0000144#define flush_cpu_data_by_index(_ix, _m) \
Soby Mathewa0fedc42016-06-16 14:52:04 +0100145 flush_dcache_range((uintptr_t) \
Soby Mathew7d861ea2014-11-18 10:14:14 +0000146 &(_cpu_data_by_index(_ix)->_m), \
147 sizeof(_cpu_data_by_index(_ix)->_m))
Achin Guptae4b9fa42014-07-25 14:47:05 +0100148
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100149
150#endif /* __ASSEMBLY__ */
151#endif /* __CPU_DATA_H__ */