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Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01001/*
Antonio Nino Diaz4357b412016-02-23 12:04:58 +00002 * Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __EL3_COMMON_MACROS_S__
32#define __EL3_COMMON_MACROS_S__
33
34#include <arch.h>
35#include <asm_macros.S>
36
37 /*
38 * Helper macro to initialise EL3 registers we care about.
39 */
40 .macro el3_arch_init_common _exception_vectors
41 /* ---------------------------------------------------------------------
42 * Enable the instruction cache, stack pointer and data access alignment
43 * checks
44 * ---------------------------------------------------------------------
45 */
46 mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT)
47 mrs x0, sctlr_el3
48 orr x0, x0, x1
49 msr sctlr_el3, x0
50 isb
51
Masahiro Yamada441bfdd2016-12-25 23:36:24 +090052#ifdef IMAGE_BL31
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010053 /* ---------------------------------------------------------------------
54 * Initialise the per-cpu cache pointer to the CPU.
55 * This is done early to enable crash reporting to have access to crash
56 * stack. Since crash reporting depends on cpu_data to report the
57 * unhandled exception, not doing so can lead to recursive exceptions
58 * due to a NULL TPIDR_EL3.
59 * ---------------------------------------------------------------------
60 */
61 bl init_cpu_data_ptr
62#endif /* IMAGE_BL31 */
63
64 /* ---------------------------------------------------------------------
65 * Set the exception vectors.
66 * ---------------------------------------------------------------------
67 */
68 adr x0, \_exception_vectors
69 msr vbar_el3, x0
70 isb
71
72 /* ---------------------------------------------------------------------
Soby Mathew074e05a2016-04-04 12:34:24 +010073 * Early set RES1 bits in SCR_EL3. Set EA bit to catch both
74 * External Aborts and SError Interrupts in EL3 and also the SIF bit
75 * to disable instruction fetches from Non-secure memory.
Gerald Lejeune632d6df2016-03-22 09:29:23 +010076 * ---------------------------------------------------------------------
77 */
Soby Mathew074e05a2016-04-04 12:34:24 +010078 mov x0, #(SCR_RES1_BITS | SCR_EA_BIT | SCR_SIF_BIT)
Gerald Lejeune632d6df2016-03-22 09:29:23 +010079 msr scr_el3, x0
David Cunado5f55e282016-10-31 17:37:34 +000080
81 /* ---------------------------------------------------------------------
82 * Reset registers that may have architecturally unknown reset values
83 * ---------------------------------------------------------------------
84 */
85 msr mdcr_el3, xzr
86
Gerald Lejeune632d6df2016-03-22 09:29:23 +010087 /* ---------------------------------------------------------------------
88 * Enable External Aborts and SError Interrupts now that the exception
89 * vectors have been setup.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +010090 * ---------------------------------------------------------------------
91 */
92 msr daifclr, #DAIF_ABT_BIT
93
94 /* ---------------------------------------------------------------------
95 * The initial state of the Architectural feature trap register
96 * (CPTR_EL3) is unknown and it must be set to a known state. All
97 * feature traps are disabled. Some bits in this register are marked as
98 * reserved and should not be modified.
99 *
100 * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1
101 * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2.
102 *
103 * CPTR_EL3.TTA: This causes access to the Trace functionality to trap
104 * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register
105 * access to trace functionality is not supported, this bit is RES0.
106 *
107 * CPTR_EL3.TFP: This causes instructions that access the registers
108 * associated with Floating Point and Advanced SIMD execution to trap
109 * to EL3 when executed from any exception level, unless trapped to EL1
110 * or EL2.
111 * ---------------------------------------------------------------------
112 */
113 mrs x0, cptr_el3
114 bic w0, w0, #TCPAC_BIT
115 bic w0, w0, #TTA_BIT
116 bic w0, w0, #TFP_BIT
117 msr cptr_el3, x0
118 .endm
119
120/* -----------------------------------------------------------------------------
121 * This is the super set of actions that need to be performed during a cold boot
Juan Castillo7d199412015-12-14 09:35:25 +0000122 * or a warm boot in EL3. This code is shared by BL1 and BL31.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100123 *
124 * This macro will always perform reset handling, architectural initialisations
125 * and stack setup. The rest of the actions are optional because they might not
126 * be needed, depending on the context in which this macro is called. This is
127 * why this macro is parameterised ; each parameter allows to enable/disable
128 * some actions.
129 *
130 * _set_endian:
131 * Whether the macro needs to configure the endianness of data accesses.
132 *
133 * _warm_boot_mailbox:
134 * Whether the macro needs to detect the type of boot (cold/warm). The
135 * detection is based on the platform entrypoint address : if it is zero
136 * then it is a cold boot, otherwise it is a warm boot. In the latter case,
137 * this macro jumps on the platform entrypoint address.
138 *
139 * _secondary_cold_boot:
140 * Whether the macro needs to identify the CPU that is calling it: primary
141 * CPU or secondary CPU. The primary CPU will be allowed to carry on with
142 * the platform initialisations, while the secondaries will be put in a
143 * platform-specific state in the meantime.
144 *
145 * If the caller knows this macro will only be called by the primary CPU
146 * then this parameter can be defined to 0 to skip this step.
147 *
148 * _init_memory:
149 * Whether the macro needs to initialise the memory.
150 *
151 * _init_c_runtime:
152 * Whether the macro needs to initialise the C runtime environment.
153 *
154 * _exception_vectors:
155 * Address of the exception vectors to program in the VBAR_EL3 register.
156 * -----------------------------------------------------------------------------
157 */
158 .macro el3_entrypoint_common \
159 _set_endian, _warm_boot_mailbox, _secondary_cold_boot, \
160 _init_memory, _init_c_runtime, _exception_vectors
161
162 .if \_set_endian
163 /* -------------------------------------------------------------
164 * Set the CPU endianness before doing anything that might
165 * involve memory reads or writes.
166 * -------------------------------------------------------------
167 */
168 mrs x0, sctlr_el3
169 bic x0, x0, #SCTLR_EE_BIT
170 msr sctlr_el3, x0
171 isb
172 .endif /* _set_endian */
173
174 .if \_warm_boot_mailbox
175 /* -------------------------------------------------------------
176 * This code will be executed for both warm and cold resets.
177 * Now is the time to distinguish between the two.
178 * Query the platform entrypoint address and if it is not zero
179 * then it means it is a warm boot so jump to this address.
180 * -------------------------------------------------------------
181 */
Soby Mathew3700a922015-07-13 11:21:11 +0100182 bl plat_get_my_entrypoint
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100183 cbz x0, do_cold_boot
184 br x0
185
186 do_cold_boot:
187 .endif /* _warm_boot_mailbox */
188
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000189 /* ---------------------------------------------------------------------
190 * It is a cold boot.
191 * Perform any processor specific actions upon reset e.g. cache, TLB
192 * invalidations etc.
193 * ---------------------------------------------------------------------
194 */
195 bl reset_handler
196
197 el3_arch_init_common \_exception_vectors
198
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100199 .if \_secondary_cold_boot
200 /* -------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000201 * Check if this is a primary or secondary CPU cold boot.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100202 * The primary CPU will set up the platform while the
203 * secondaries are placed in a platform-specific state until the
204 * primary CPU performs the necessary actions to bring them out
205 * of that state and allows entry into the OS.
206 * -------------------------------------------------------------
207 */
Soby Mathew3700a922015-07-13 11:21:11 +0100208 bl plat_is_my_cpu_primary
Soby Matheweb3bbf12015-06-08 12:32:50 +0100209 cbnz w0, do_primary_cold_boot
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100210
211 /* This is a cold boot on a secondary CPU */
212 bl plat_secondary_cold_boot_setup
213 /* plat_secondary_cold_boot_setup() is not supposed to return */
Antonio Nino Diaz1f21bcf2016-02-01 13:57:25 +0000214 bl el3_panic
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100215
216 do_primary_cold_boot:
217 .endif /* _secondary_cold_boot */
218
219 /* ---------------------------------------------------------------------
Antonio Nino Diaz4357b412016-02-23 12:04:58 +0000220 * Initialize memory now. Secondary CPU initialization won't get to this
221 * point.
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100222 * ---------------------------------------------------------------------
223 */
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100224
225 .if \_init_memory
226 bl platform_mem_init
227 .endif /* _init_memory */
228
229 /* ---------------------------------------------------------------------
230 * Init C runtime environment:
231 * - Zero-initialise the NOBITS sections. There are 2 of them:
232 * - the .bss section;
233 * - the coherent memory section (if any).
234 * - Relocate the data section from ROM to RAM, if required.
235 * ---------------------------------------------------------------------
236 */
237 .if \_init_c_runtime
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900238#ifdef IMAGE_BL31
Achin Guptae9c4a642015-09-11 16:03:13 +0100239 /* -------------------------------------------------------------
240 * Invalidate the RW memory used by the BL31 image. This
241 * includes the data and NOBITS sections. This is done to
242 * safeguard against possible corruption of this memory by
243 * dirty cache lines in a system cache as a result of use by
244 * an earlier boot loader stage.
245 * -------------------------------------------------------------
246 */
247 adr x0, __RW_START__
248 adr x1, __RW_END__
249 sub x1, x1, x0
250 bl inv_dcache_range
251#endif /* IMAGE_BL31 */
252
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100253 ldr x0, =__BSS_START__
254 ldr x1, =__BSS_SIZE__
255 bl zeromem16
256
257#if USE_COHERENT_MEM
258 ldr x0, =__COHERENT_RAM_START__
259 ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__
260 bl zeromem16
261#endif
262
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900263#ifdef IMAGE_BL1
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100264 ldr x0, =__DATA_RAM_START__
265 ldr x1, =__DATA_ROM_START__
266 ldr x2, =__DATA_SIZE__
267 bl memcpy16
268#endif
269 .endif /* _init_c_runtime */
270
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100271 /* ---------------------------------------------------------------------
272 * Use SP_EL0 for the C runtime stack.
273 * ---------------------------------------------------------------------
274 */
275 msr spsel, #0
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100276
277 /* ---------------------------------------------------------------------
278 * Allocate a stack whose memory will be marked as Normal-IS-WBWA when
279 * the MMU is enabled. There is no risk of reading stale stack memory
280 * after enabling the MMU as only the primary CPU is running at the
281 * moment.
282 * ---------------------------------------------------------------------
283 */
Soby Mathew3700a922015-07-13 11:21:11 +0100284 bl plat_set_my_stack
Sandrine Bailleuxacde8b02015-05-19 11:54:45 +0100285 .endm
286
287#endif /* __EL3_COMMON_MACROS_S__ */