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Jacky Baia6177002019-03-06 17:15:06 +08001/*
Jacky Bai0e400552022-03-14 17:14:26 +08002 * Copyright (c) 2019-2022 ARM Limited and Contributors. All rights reserved.
Jacky Baia6177002019-03-06 17:15:06 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <assert.h>
8#include <stdbool.h>
9
10#include <platform_def.h>
11
12#include <arch_helpers.h>
13#include <common/bl_common.h>
14#include <common/debug.h>
15#include <context.h>
16#include <drivers/arm/tzc380.h>
17#include <drivers/console.h>
18#include <drivers/generic_delay_timer.h>
19#include <lib/el3_runtime/context_mgmt.h>
20#include <lib/mmio.h>
Ji Luoe329b3d2020-02-20 23:47:21 +080021#include <lib/xlat_tables/xlat_tables_v2.h>
Jacky Baia6177002019-03-06 17:15:06 +080022#include <plat/common/platform.h>
23
Jacky Baiec031802019-11-25 14:45:32 +080024#include <dram.h>
Jacky Baia6177002019-03-06 17:15:06 +080025#include <gpc.h>
Jacky Bai91c6d322019-05-21 20:24:52 +080026#include <imx_aipstz.h>
Jacky Baia6177002019-03-06 17:15:06 +080027#include <imx_uart.h>
Jacky Bai64130a32019-07-18 13:43:17 +080028#include <imx_rdc.h>
Jacky Bai3bf04a52019-06-12 17:41:47 +080029#include <imx8m_caam.h>
Jacky Bai3c3c2682020-01-07 14:53:54 +080030#include <imx8m_csu.h>
Jacky Baia6177002019-03-06 17:15:06 +080031#include <plat_imx8.h>
32
Ji Luo1c33a2e2020-02-21 10:36:47 +080033#define TRUSTY_PARAMS_LEN_BYTES (4096*2)
34
Jacky Baia6177002019-03-06 17:15:06 +080035static const mmap_region_t imx_mmap[] = {
36 MAP_REGION_FLAT(IMX_GIC_BASE, IMX_GIC_SIZE, MT_DEVICE | MT_RW),
37 MAP_REGION_FLAT(IMX_AIPS_BASE, IMX_AIPS_SIZE, MT_DEVICE | MT_RW), /* AIPS map */
Jacky Baiec031802019-11-25 14:45:32 +080038 MAP_REGION_FLAT(OCRAM_S_BASE, OCRAM_S_SIZE, MT_DEVICE | MT_RW), /* OCRAM_S */
39 MAP_REGION_FLAT(IMX_DDRPHY_BASE, IMX_DDR_IPS_SIZE, MT_DEVICE | MT_RW), /* DDRMIX */
Jacky Bai31f02322019-12-11 16:26:59 +080040 MAP_REGION_FLAT(IMX_VPUMIX_BASE, IMX_VPUMIX_SIZE, MT_DEVICE | MT_RW), /* VPUMIX */
Jacky Baia6177002019-03-06 17:15:06 +080041 {0},
42};
43
Jacky Bai91c6d322019-05-21 20:24:52 +080044static const struct aipstz_cfg aipstz[] = {
45 {IMX_AIPSTZ1, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
46 {IMX_AIPSTZ2, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
47 {IMX_AIPSTZ3, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
48 {IMX_AIPSTZ4, 0x77777777, 0x77777777, .opacr = {0x0, 0x0, 0x0, 0x0, 0x0}, },
49 {0},
50};
51
Jacky Bai64130a32019-07-18 13:43:17 +080052static const struct imx_rdc_cfg rdc[] = {
53 /* Master domain assignment */
Jacky Bai0e400552022-03-14 17:14:26 +080054 RDC_MDAn(RDC_MDA_M4, DID1),
Jacky Bai64130a32019-07-18 13:43:17 +080055
56 /* peripherals domain permission */
Jacky Bai0e400552022-03-14 17:14:26 +080057 RDC_PDAPn(RDC_PDAP_UART4, D1R | D1W),
58 RDC_PDAPn(RDC_PDAP_UART2, D0R | D0W),
Jacky Bai64130a32019-07-18 13:43:17 +080059
60 /* memory region */
61
62 /* Sentinel */
63 {0},
64};
65
Jacky Bai3c3c2682020-01-07 14:53:54 +080066static const struct imx_csu_cfg csu_cfg[] = {
67 /* peripherals csl setting */
68 CSU_CSLx(0x1, CSU_SEC_LEVEL_0, UNLOCKED),
69
70 /* master HP0~1 */
71
72 /* SA setting */
73
74 /* HP control setting */
75
76 /* Sentinel */
77 {0}
78};
79
Jacky Baia6177002019-03-06 17:15:06 +080080static entry_point_info_t bl32_image_ep_info;
81static entry_point_info_t bl33_image_ep_info;
82
83/* get SPSR for BL33 entry */
84static uint32_t get_spsr_for_bl33_entry(void)
85{
86 unsigned long el_status;
87 unsigned long mode;
88 uint32_t spsr;
89
90 /* figure out what mode we enter the non-secure world */
91 el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
92 el_status &= ID_AA64PFR0_ELX_MASK;
93
94 mode = (el_status) ? MODE_EL2 : MODE_EL1;
95
96 spsr = SPSR_64(mode, MODE_SP_ELX, DISABLE_ALL_EXCEPTIONS);
97 return spsr;
98}
99
100void bl31_tzc380_setup(void)
101{
102 unsigned int val;
103
104 val = mmio_read_32(IMX_IOMUX_GPR_BASE + 0x28);
105 if ((val & GPR_TZASC_EN) != GPR_TZASC_EN)
106 return;
107
108 tzc380_init(IMX_TZASC_BASE);
109
110 /*
111 * Need to substact offset 0x40000000 from CPU address when
112 * programming tzasc region for i.mx8mm.
113 */
114
115 /* Enable 1G-5G S/NS RW */
116 tzc380_configure_region(0, 0x00000000, TZC_ATTR_REGION_SIZE(TZC_REGION_SIZE_4G) |
117 TZC_ATTR_REGION_EN_MASK | TZC_ATTR_SP_ALL);
118}
119
120void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
121 u_register_t arg2, u_register_t arg3)
122{
Andre Przywara7110d992020-01-25 00:58:35 +0000123 static console_t console;
Jacky Baia6177002019-03-06 17:15:06 +0800124 int i;
125
126 /* Enable CSU NS access permission */
127 for (i = 0; i < 64; i++) {
128 mmio_write_32(IMX_CSU_BASE + i * 4, 0x00ff00ff);
129 }
130
Jacky Bai91c6d322019-05-21 20:24:52 +0800131 imx_aipstz_init(aipstz);
Jacky Baia6177002019-03-06 17:15:06 +0800132
Jacky Bai64130a32019-07-18 13:43:17 +0800133 imx_rdc_init(rdc);
134
Jacky Bai3c3c2682020-01-07 14:53:54 +0800135 imx_csu_init(csu_cfg);
136
Jacky Baia6177002019-03-06 17:15:06 +0800137 console_imx_uart_register(IMX_BOOT_UART_BASE, IMX_BOOT_UART_CLK_IN_HZ,
138 IMX_CONSOLE_BAUDRATE, &console);
139 /* This console is only used for boot stage */
Andre Przywara7110d992020-01-25 00:58:35 +0000140 console_set_scope(&console, CONSOLE_FLAG_BOOT);
Jacky Baia6177002019-03-06 17:15:06 +0800141
Andrey Zhizhikin6651ef82022-09-19 20:49:16 +0200142 imx8m_caam_init();
143
Jacky Baia6177002019-03-06 17:15:06 +0800144 /*
145 * tell BL3-1 where the non-secure software image is located
146 * and the entry state information.
147 */
148 bl33_image_ep_info.pc = PLAT_NS_IMAGE_OFFSET;
149 bl33_image_ep_info.spsr = get_spsr_for_bl33_entry();
150 SET_SECURITY_STATE(bl33_image_ep_info.h.attr, NON_SECURE);
151
Ji Luo1c33a2e2020-02-21 10:36:47 +0800152#if defined(SPD_opteed) || defined(SPD_trusty)
Jacky Bai2a763ba2019-07-18 13:34:09 +0800153 /* Populate entry point information for BL32 */
154 SET_PARAM_HEAD(&bl32_image_ep_info, PARAM_EP, VERSION_1, 0);
155 SET_SECURITY_STATE(bl32_image_ep_info.h.attr, SECURE);
156 bl32_image_ep_info.pc = BL32_BASE;
157 bl32_image_ep_info.spsr = 0;
158
Silvano di Ninnob723a552020-03-25 09:24:51 +0100159 /* Pass TEE base and size to bl33 */
160 bl33_image_ep_info.args.arg1 = BL32_BASE;
161 bl33_image_ep_info.args.arg2 = BL32_SIZE;
162
Ji Luo1c33a2e2020-02-21 10:36:47 +0800163#ifdef SPD_trusty
164 bl32_image_ep_info.args.arg0 = BL32_SIZE;
165 bl32_image_ep_info.args.arg1 = BL32_BASE;
Silvano di Ninnob723a552020-03-25 09:24:51 +0100166#else
167 /* Make sure memory is clean */
168 mmio_write_32(BL32_FDT_OVERLAY_ADDR, 0);
169 bl33_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
170 bl32_image_ep_info.args.arg3 = BL32_FDT_OVERLAY_ADDR;
Ji Luo1c33a2e2020-02-21 10:36:47 +0800171#endif
Jacky Bai2a763ba2019-07-18 13:34:09 +0800172#endif
173
Jacky Baia6177002019-03-06 17:15:06 +0800174 bl31_tzc380_setup();
175}
176
177void bl31_plat_arch_setup(void)
178{
179 mmap_add_region(BL31_BASE, BL31_BASE, (BL31_LIMIT - BL31_BASE),
180 MT_MEMORY | MT_RW | MT_SECURE);
181 mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, (BL_CODE_END - BL_CODE_BASE),
182 MT_MEMORY | MT_RO | MT_SECURE);
183#if USE_COHERENT_MEM
184 mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE,
185 (BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE),
186 MT_DEVICE | MT_RW | MT_SECURE);
187#endif
Ji Luo1c33a2e2020-02-21 10:36:47 +0800188 /* Map TEE memory */
189 mmap_add_region(BL32_BASE, BL32_BASE, BL32_SIZE, MT_MEMORY | MT_RW);
190
Jacky Baia6177002019-03-06 17:15:06 +0800191 mmap_add(imx_mmap);
192
193 init_xlat_tables();
194
195 enable_mmu_el3(0);
196}
197
198void bl31_platform_setup(void)
199{
200 generic_delay_timer_init();
201
202 /* select the CKIL source to 32K OSC */
203 mmio_write_32(IMX_ANAMIX_BASE + ANAMIX_MISC_CTL, 0x1);
204
Jacky Baiec031802019-11-25 14:45:32 +0800205 /* Init the dram info */
206 dram_info_init(SAVED_DRAM_TIMING_BASE);
207
Jacky Baia6177002019-03-06 17:15:06 +0800208 plat_gic_driver_init();
209 plat_gic_init();
210
211 imx_gpc_init();
212}
213
214entry_point_info_t *bl31_plat_get_next_image_ep_info(unsigned int type)
215{
216 if (type == NON_SECURE)
217 return &bl33_image_ep_info;
218 if (type == SECURE)
219 return &bl32_image_ep_info;
220
221 return NULL;
222}
223
224unsigned int plat_get_syscnt_freq2(void)
225{
226 return COUNTER_FREQUENCY;
227}
Ji Luo1c33a2e2020-02-21 10:36:47 +0800228
229#ifdef SPD_trusty
230void plat_trusty_set_boot_args(aapcs64_params_t *args)
231{
232 args->arg0 = BL32_SIZE;
233 args->arg1 = BL32_BASE;
234 args->arg2 = TRUSTY_PARAMS_LEN_BYTES;
235}
236#endif