Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 1 | /* |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved. |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <platform_def.h> |
| 10 | |
| 11 | #include <common/debug.h> |
| 12 | #include <drivers/arm/tzc400.h> |
| 13 | #include <drivers/st/stm32mp1_clk.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 14 | #include <dt-bindings/clock/stm32mp1-clks.h> |
| 15 | #include <lib/mmio.h> |
| 16 | |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 17 | #define TZC_REGION_NSEC_ALL_ACCESS_RDWR \ |
| 18 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | \ |
| 19 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_GPU_ID) | \ |
| 20 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_LCD_ID) | \ |
| 21 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_MDMA_ID) | \ |
| 22 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_M4_ID) | \ |
| 23 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DMA_ID) | \ |
| 24 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_HOST_ID) | \ |
| 25 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_USB_OTG_ID) | \ |
| 26 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID) | \ |
| 27 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_ETH_ID) | \ |
| 28 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_DAP_ID) |
| 29 | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 30 | /******************************************************************************* |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 31 | * Initialize the TrustZone Controller. Configure Region 0 with Secure RW access |
| 32 | * and allow Non-Secure masters full access. |
| 33 | ******************************************************************************/ |
| 34 | static void init_tzc400(void) |
| 35 | { |
| 36 | unsigned long long region_base, region_top; |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 37 | unsigned long long ddr_base = STM32MP_DDR_BASE; |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 38 | unsigned long long ddr_size = (unsigned long long)dt_get_ddr_size(); |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 39 | unsigned long long ddr_top = ddr_base + (ddr_size - 1U); |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 40 | |
| 41 | tzc400_init(STM32MP1_TZC_BASE); |
| 42 | |
| 43 | tzc400_disable_filters(); |
| 44 | |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 45 | #ifdef AARCH32_SP_OPTEE |
| 46 | /* |
| 47 | * Region 1 set to cover all non-secure DRAM at 0xC000_0000. Apply the |
| 48 | * same configuration to all filters in the TZC. |
| 49 | */ |
| 50 | region_base = ddr_base; |
| 51 | region_top = ddr_top - STM32MP_DDR_S_SIZE - STM32MP_DDR_SHMEM_SIZE; |
| 52 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1, |
| 53 | region_base, |
| 54 | region_top, |
| 55 | TZC_REGION_S_NONE, |
| 56 | TZC_REGION_NSEC_ALL_ACCESS_RDWR); |
| 57 | |
| 58 | /* Region 2 set to cover all secure DRAM. */ |
| 59 | region_base = region_top + 1U; |
| 60 | region_top = ddr_top - STM32MP_DDR_SHMEM_SIZE; |
| 61 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 2, |
| 62 | region_base, |
| 63 | region_top, |
| 64 | TZC_REGION_S_RDWR, |
| 65 | 0); |
| 66 | |
| 67 | /* Region 3 set to cover non-secure shared memory DRAM. */ |
| 68 | region_base = region_top + 1U; |
| 69 | region_top = ddr_top; |
| 70 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 3, |
| 71 | region_base, |
| 72 | region_top, |
| 73 | TZC_REGION_S_NONE, |
| 74 | TZC_REGION_NSEC_ALL_ACCESS_RDWR); |
| 75 | #else |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 76 | /* |
| 77 | * Region 1 set to cover all DRAM at 0xC000_0000. Apply the |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 78 | * same configuration to all filters in the TZC. |
| 79 | */ |
| 80 | region_base = ddr_base; |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 81 | region_top = ddr_top; |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 82 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1, |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 83 | region_base, |
| 84 | region_top, |
| 85 | TZC_REGION_S_NONE, |
| 86 | TZC_REGION_NSEC_ALL_ACCESS_RDWR); |
Yann Gautier | b3386f7 | 2019-04-19 09:41:01 +0200 | [diff] [blame] | 87 | #endif |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 88 | |
| 89 | /* Raise an exception if a NS device tries to access secure memory */ |
| 90 | tzc400_set_action(TZC_ACTION_ERR); |
| 91 | |
| 92 | tzc400_enable_filters(); |
| 93 | } |
| 94 | |
| 95 | /******************************************************************************* |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 96 | * Initialize the TrustZone Controller. |
| 97 | * Early initialization create only one region with full access to secure. |
| 98 | * This setting is used before and during DDR initialization. |
| 99 | ******************************************************************************/ |
| 100 | static void early_init_tzc400(void) |
| 101 | { |
Yann Gautier | e4a3c35 | 2019-02-14 10:53:33 +0100 | [diff] [blame] | 102 | stm32mp_clk_enable(TZC1); |
| 103 | stm32mp_clk_enable(TZC2); |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 104 | |
| 105 | tzc400_init(STM32MP1_TZC_BASE); |
| 106 | |
| 107 | tzc400_disable_filters(); |
| 108 | |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 109 | /* Region 1 set to cover Non-Secure DRAM at 0xC000_0000 */ |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 110 | tzc400_configure_region(STM32MP1_FILTER_BIT_ALL, 1, |
Yann Gautier | a2e2a30 | 2019-02-14 11:13:39 +0100 | [diff] [blame] | 111 | STM32MP_DDR_BASE, |
| 112 | STM32MP_DDR_BASE + |
| 113 | (STM32MP_DDR_MAX_SIZE - 1U), |
Yann Gautier | e3de4c0 | 2019-04-18 15:32:10 +0200 | [diff] [blame] | 114 | TZC_REGION_S_NONE, |
Yann Gautier | f9d40d5 | 2019-01-17 14:41:46 +0100 | [diff] [blame] | 115 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_A7_ID) | |
Yann Gautier | caf575b | 2018-07-24 17:18:19 +0200 | [diff] [blame] | 116 | TZC_REGION_ACCESS_RDWR(STM32MP1_TZC_SDMMC_ID)); |
| 117 | |
| 118 | /* Raise an exception if a NS device tries to access secure memory */ |
| 119 | tzc400_set_action(TZC_ACTION_ERR); |
| 120 | |
| 121 | tzc400_enable_filters(); |
| 122 | } |
| 123 | |
| 124 | /******************************************************************************* |
| 125 | * Initialize the secure environment. At this moment only the TrustZone |
| 126 | * Controller is initialized. |
| 127 | ******************************************************************************/ |
| 128 | void stm32mp1_arch_security_setup(void) |
| 129 | { |
| 130 | early_init_tzc400(); |
| 131 | } |
Yann Gautier | 9d135e4 | 2018-07-16 19:36:06 +0200 | [diff] [blame] | 132 | |
| 133 | /******************************************************************************* |
| 134 | * Initialize the secure environment. At this moment only the TrustZone |
| 135 | * Controller is initialized. |
| 136 | ******************************************************************************/ |
| 137 | void stm32mp1_security_setup(void) |
| 138 | { |
| 139 | init_tzc400(); |
| 140 | } |