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Sandrine Bailleux27866d82013-10-25 15:33:39 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux27866d82013-10-25 15:33:39 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __GIC_V2_H__
32#define __GIC_V2_H__
33
Dan Handley930ee2e2014-04-17 17:48:52 +010034
35#define GIC400_NUM_SPIS 480
36#define MAX_PPIS 14
37#define MAX_SGIS 16
38
Dan Handleyfb42b122014-06-20 09:43:15 +010039#define MIN_SGI_ID 0
40#define MIN_PPI_ID 16
41#define MIN_SPI_ID 32
42
Dan Handley930ee2e2014-04-17 17:48:52 +010043#define GRP0 0
44#define GRP1 1
45#define GIC_PRI_MASK 0xff
46#define GIC_HIGHEST_SEC_PRIORITY 0
47#define GIC_LOWEST_SEC_PRIORITY 127
48#define GIC_HIGHEST_NS_PRIORITY 128
49#define GIC_LOWEST_NS_PRIORITY 254 /* 255 would disable an interrupt */
Achin Gupta02d36282014-05-04 19:02:52 +010050#define GIC_SPURIOUS_INTERRUPT 1023
Dan Handley930ee2e2014-04-17 17:48:52 +010051
52#define ENABLE_GRP0 (1 << 0)
53#define ENABLE_GRP1 (1 << 1)
54
55/* Distributor interface definitions */
56#define GICD_CTLR 0x0
57#define GICD_TYPER 0x4
58#define GICD_IGROUPR 0x80
59#define GICD_ISENABLER 0x100
60#define GICD_ICENABLER 0x180
61#define GICD_ISPENDR 0x200
62#define GICD_ICPENDR 0x280
63#define GICD_ISACTIVER 0x300
64#define GICD_ICACTIVER 0x380
65#define GICD_IPRIORITYR 0x400
66#define GICD_ITARGETSR 0x800
67#define GICD_ICFGR 0xC00
68#define GICD_SGIR 0xF00
69#define GICD_CPENDSGIR 0xF10
70#define GICD_SPENDSGIR 0xF20
71
72#define IGROUPR_SHIFT 5
73#define ISENABLER_SHIFT 5
74#define ICENABLER_SHIFT ISENABLER_SHIFT
75#define ISPENDR_SHIFT 5
76#define ICPENDR_SHIFT ISPENDR_SHIFT
77#define ISACTIVER_SHIFT 5
78#define ICACTIVER_SHIFT ISACTIVER_SHIFT
79#define IPRIORITYR_SHIFT 2
80#define ITARGETSR_SHIFT 2
81#define ICFGR_SHIFT 4
82#define CPENDSGIR_SHIFT 2
83#define SPENDSGIR_SHIFT CPENDSGIR_SHIFT
84
85/* GICD_TYPER bit definitions */
86#define IT_LINES_NO_MASK 0x1f
87
88/* Physical CPU Interface registers */
89#define GICC_CTLR 0x0
90#define GICC_PMR 0x4
91#define GICC_BPR 0x8
92#define GICC_IAR 0xC
93#define GICC_EOIR 0x10
94#define GICC_RPR 0x14
95#define GICC_HPPIR 0x18
Achin Gupta02d36282014-05-04 19:02:52 +010096#define GICC_AHPPIR 0x28
Dan Handley930ee2e2014-04-17 17:48:52 +010097#define GICC_IIDR 0xFC
98#define GICC_DIR 0x1000
99#define GICC_PRIODROP GICC_EOIR
100
101/* GICC_CTLR bit definitions */
102#define EOI_MODE_NS (1 << 10)
103#define EOI_MODE_S (1 << 9)
104#define IRQ_BYP_DIS_GRP1 (1 << 8)
105#define FIQ_BYP_DIS_GRP1 (1 << 7)
106#define IRQ_BYP_DIS_GRP0 (1 << 6)
107#define FIQ_BYP_DIS_GRP0 (1 << 5)
108#define CBPR (1 << 4)
109#define FIQ_EN (1 << 3)
110#define ACK_CTL (1 << 2)
111
112/* GICC_IIDR bit masks and shifts */
113#define GICC_IIDR_PID_SHIFT 20
114#define GICC_IIDR_ARCH_SHIFT 16
115#define GICC_IIDR_REV_SHIFT 12
116#define GICC_IIDR_IMP_SHIFT 0
117
118#define GICC_IIDR_PID_MASK 0xfff
119#define GICC_IIDR_ARCH_MASK 0xf
120#define GICC_IIDR_REV_MASK 0xf
121#define GICC_IIDR_IMP_MASK 0xfff
122
123/* HYP view virtual CPU Interface registers */
124#define GICH_CTL 0x0
125#define GICH_VTR 0x4
126#define GICH_ELRSR0 0x30
127#define GICH_ELRSR1 0x34
128#define GICH_APR0 0xF0
129#define GICH_LR_BASE 0x100
130
131/* Virtual CPU Interface registers */
132#define GICV_CTL 0x0
133#define GICV_PRIMASK 0x4
134#define GICV_BP 0x8
135#define GICV_INTACK 0xC
136#define GICV_EOI 0x10
137#define GICV_RUNNINGPRI 0x14
138#define GICV_HIGHESTPEND 0x18
139#define GICV_DEACTIVATE 0x1000
140
141#ifndef __ASSEMBLY__
142
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100143#include <mmio.h>
144
Dan Handley930ee2e2014-04-17 17:48:52 +0100145
146/*******************************************************************************
147 * GIC Distributor function prototypes
148 ******************************************************************************/
149
Dan Handleya17fefa2014-05-14 12:38:32 +0100150unsigned int gicd_read_igroupr(unsigned int, unsigned int);
151unsigned int gicd_read_isenabler(unsigned int, unsigned int);
152unsigned int gicd_read_icenabler(unsigned int, unsigned int);
153unsigned int gicd_read_ispendr(unsigned int, unsigned int);
154unsigned int gicd_read_icpendr(unsigned int, unsigned int);
155unsigned int gicd_read_isactiver(unsigned int, unsigned int);
156unsigned int gicd_read_icactiver(unsigned int, unsigned int);
157unsigned int gicd_read_ipriorityr(unsigned int, unsigned int);
158unsigned int gicd_read_itargetsr(unsigned int, unsigned int);
159unsigned int gicd_read_icfgr(unsigned int, unsigned int);
160unsigned int gicd_read_cpendsgir(unsigned int, unsigned int);
161unsigned int gicd_read_spendsgir(unsigned int, unsigned int);
162void gicd_write_igroupr(unsigned int, unsigned int, unsigned int);
163void gicd_write_isenabler(unsigned int, unsigned int, unsigned int);
164void gicd_write_icenabler(unsigned int, unsigned int, unsigned int);
165void gicd_write_ispendr(unsigned int, unsigned int, unsigned int);
166void gicd_write_icpendr(unsigned int, unsigned int, unsigned int);
167void gicd_write_isactiver(unsigned int, unsigned int, unsigned int);
168void gicd_write_icactiver(unsigned int, unsigned int, unsigned int);
169void gicd_write_ipriorityr(unsigned int, unsigned int, unsigned int);
170void gicd_write_itargetsr(unsigned int, unsigned int, unsigned int);
171void gicd_write_icfgr(unsigned int, unsigned int, unsigned int);
172void gicd_write_cpendsgir(unsigned int, unsigned int, unsigned int);
173void gicd_write_spendsgir(unsigned int, unsigned int, unsigned int);
174unsigned int gicd_get_igroupr(unsigned int, unsigned int);
175void gicd_set_igroupr(unsigned int, unsigned int);
176void gicd_clr_igroupr(unsigned int, unsigned int);
177void gicd_set_isenabler(unsigned int, unsigned int);
178void gicd_set_icenabler(unsigned int, unsigned int);
179void gicd_set_ispendr(unsigned int, unsigned int);
180void gicd_set_icpendr(unsigned int, unsigned int);
181void gicd_set_isactiver(unsigned int, unsigned int);
182void gicd_set_icactiver(unsigned int, unsigned int);
183void gicd_set_ipriorityr(unsigned int, unsigned int, unsigned int);
184void gicd_set_itargetsr(unsigned int, unsigned int, unsigned int);
Dan Handley930ee2e2014-04-17 17:48:52 +0100185
186
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100187/*******************************************************************************
188 * GIC Distributor interface accessors for reading entire registers
189 ******************************************************************************/
190
191static inline unsigned int gicd_read_ctlr(unsigned int base)
192{
193 return mmio_read_32(base + GICD_CTLR);
194}
195
196static inline unsigned int gicd_read_typer(unsigned int base)
197{
198 return mmio_read_32(base + GICD_TYPER);
199}
200
201static inline unsigned int gicd_read_sgir(unsigned int base)
202{
203 return mmio_read_32(base + GICD_SGIR);
204}
205
206
207/*******************************************************************************
208 * GIC Distributor interface accessors for writing entire registers
209 ******************************************************************************/
210
211static inline void gicd_write_ctlr(unsigned int base, unsigned int val)
212{
213 mmio_write_32(base + GICD_CTLR, val);
214}
215
216static inline void gicd_write_sgir(unsigned int base, unsigned int val)
217{
218 mmio_write_32(base + GICD_SGIR, val);
219}
220
221
222/*******************************************************************************
223 * GIC CPU interface accessors for reading entire registers
224 ******************************************************************************/
225
226static inline unsigned int gicc_read_ctlr(unsigned int base)
227{
228 return mmio_read_32(base + GICC_CTLR);
229}
230
231static inline unsigned int gicc_read_pmr(unsigned int base)
232{
233 return mmio_read_32(base + GICC_PMR);
234}
235
236static inline unsigned int gicc_read_BPR(unsigned int base)
237{
238 return mmio_read_32(base + GICC_BPR);
239}
240
241static inline unsigned int gicc_read_IAR(unsigned int base)
242{
243 return mmio_read_32(base + GICC_IAR);
244}
245
246static inline unsigned int gicc_read_EOIR(unsigned int base)
247{
248 return mmio_read_32(base + GICC_EOIR);
249}
250
251static inline unsigned int gicc_read_hppir(unsigned int base)
252{
253 return mmio_read_32(base + GICC_HPPIR);
254}
255
Achin Gupta02d36282014-05-04 19:02:52 +0100256static inline unsigned int gicc_read_ahppir(unsigned int base)
257{
258 return mmio_read_32(base + GICC_AHPPIR);
259}
260
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100261static inline unsigned int gicc_read_dir(unsigned int base)
262{
263 return mmio_read_32(base + GICC_DIR);
264}
265
266static inline unsigned int gicc_read_iidr(unsigned int base)
267{
268 return mmio_read_32(base + GICC_IIDR);
269}
270
271
272/*******************************************************************************
273 * GIC CPU interface accessors for writing entire registers
274 ******************************************************************************/
275
276static inline void gicc_write_ctlr(unsigned int base, unsigned int val)
277{
278 mmio_write_32(base + GICC_CTLR, val);
279}
280
281static inline void gicc_write_pmr(unsigned int base, unsigned int val)
282{
283 mmio_write_32(base + GICC_PMR, val);
284}
285
286static inline void gicc_write_BPR(unsigned int base, unsigned int val)
287{
288 mmio_write_32(base + GICC_BPR, val);
289}
290
291
292static inline void gicc_write_IAR(unsigned int base, unsigned int val)
293{
294 mmio_write_32(base + GICC_IAR, val);
295}
296
297static inline void gicc_write_EOIR(unsigned int base, unsigned int val)
298{
299 mmio_write_32(base + GICC_EOIR, val);
300}
301
302static inline void gicc_write_hppir(unsigned int base, unsigned int val)
303{
304 mmio_write_32(base + GICC_HPPIR, val);
305}
306
307static inline void gicc_write_dir(unsigned int base, unsigned int val)
308{
309 mmio_write_32(base + GICC_DIR, val);
310}
311
Achin Gupta191e86e2014-05-09 10:03:15 +0100312/*******************************************************************************
313 * Prototype of function to map an interrupt type to the interrupt line used to
314 * signal it.
315 ******************************************************************************/
316uint32_t gicv2_interrupt_type_to_line(uint32_t cpuif_base, uint32_t type);
317
Dan Handley930ee2e2014-04-17 17:48:52 +0100318#endif /*__ASSEMBLY__*/
319
Sandrine Bailleux27866d82013-10-25 15:33:39 +0100320#endif /* __GIC_V2_H__ */