Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 1 | /* |
Biwen Li | 62e499b | 2021-01-17 14:30:33 +0800 | [diff] [blame^] | 2 | * Copyright 2021-2022 NXP |
Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_GICV3_H |
| 9 | #define PLAT_GICV3_H |
| 10 | |
| 11 | #include <drivers/arm/gicv3.h> |
| 12 | |
| 13 | /* offset between redistributors */ |
| 14 | #define GIC_RD_OFFSET 0x00020000 |
| 15 | /* offset between SGI's */ |
| 16 | #define GIC_SGI_OFFSET 0x00020000 |
| 17 | /* offset from rd base to sgi base */ |
| 18 | #define GIC_RD_2_SGI_OFFSET 0x00010000 |
| 19 | |
| 20 | /* register offsets */ |
| 21 | #define GICD_CTLR_OFFSET 0x0 |
| 22 | #define GICD_CLR_SPI_SR 0x58 |
| 23 | #define GICD_IGROUPR_2 0x88 |
Biwen Li | 62e499b | 2021-01-17 14:30:33 +0800 | [diff] [blame^] | 24 | #define GICD_ISENABLER_1 0x104 |
| 25 | #define GICD_ICENABLER_1 0x184 |
Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 26 | #define GICD_ISENABLER_2 0x108 |
| 27 | #define GICD_ICENABLER_2 0x188 |
Biwen Li | 62e499b | 2021-01-17 14:30:33 +0800 | [diff] [blame^] | 28 | #define GICD_ISENABLER_3 0x10c |
| 29 | #define GICD_ICENABLER_3 0x18c |
Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 30 | #define GICD_ICPENDR_2 0x288 |
| 31 | #define GICD_ICACTIVER_2 0x388 |
| 32 | #define GICD_IPRIORITYR_22 0x458 |
| 33 | #define GICD_ICFGR_5 0xC14 |
| 34 | #define GICD_IGRPMODR_2 0xD08 |
| 35 | |
| 36 | #define GICD_IROUTER60_OFFSET 0x61e0 |
| 37 | #define GICD_IROUTER76_OFFSET 0x6260 |
| 38 | #define GICD_IROUTER89_OFFSET 0x62C8 |
| 39 | #define GICD_IROUTER112_OFFSET 0x6380 |
| 40 | #define GICD_IROUTER113_OFFSET 0x6388 |
| 41 | |
| 42 | #define GICR_ICENABLER0_OFFSET 0x180 |
| 43 | #define GICR_CTLR_OFFSET 0x0 |
| 44 | #define GICR_IGROUPR0_OFFSET 0x80 |
| 45 | #define GICR_IGRPMODR0_OFFSET 0xD00 |
| 46 | #define GICR_IPRIORITYR3_OFFSET 0x40C |
| 47 | #define GICR_ICPENDR0_OFFSET 0x280 |
| 48 | #define GICR_ISENABLER0_OFFSET 0x100 |
| 49 | #define GICR_TYPER_OFFSET 0x8 |
| 50 | #define GICR_WAKER_OFFSET 0x14 |
| 51 | #define GICR_ICACTIVER0_OFFSET 0x380 |
| 52 | #define GICR_ICFGR0_OFFSET 0xC00 |
| 53 | |
| 54 | /* bitfield masks */ |
| 55 | #define GICD_CTLR_EN_GRP_MASK 0x7 |
| 56 | #define GICD_CTLR_EN_GRP_1NS 0x2 |
| 57 | #define GICD_CTLR_EN_GRP_1S 0x4 |
| 58 | #define GICD_CTLR_EN_GRP_0 0x1 |
| 59 | #define GICD_CTLR_ARE_S_MASK 0x10 |
| 60 | #define GICD_CTLR_RWP 0x80000000 |
| 61 | |
| 62 | #define GICR_ICENABLER0_SGI15 0x00008000 |
| 63 | #define GICR_CTLR_RWP 0x8 |
| 64 | #define GICR_CTLR_DPG0_MASK 0x2000000 |
| 65 | #define GICR_IGROUPR0_SGI15 0x00008000 |
| 66 | #define GICR_IGRPMODR0_SGI15 0x00008000 |
| 67 | #define GICR_ISENABLER0_SGI15 0x00008000 |
| 68 | #define GICR_IPRIORITYR3_SGI15_MASK 0xFF000000 |
| 69 | #define GICR_ICPENDR0_SGI15 0x8000 |
| 70 | |
| 71 | #define GIC_SPI_89_MASK 0x02000000 |
| 72 | #define GIC_SPI89_PRIORITY_MASK 0xFF00 |
| 73 | #define GIC_IRM_SPI89 0x80000000 |
| 74 | |
| 75 | #define GICD_IROUTER_VALUE 0x100 |
Biwen Li | 62e499b | 2021-01-17 14:30:33 +0800 | [diff] [blame^] | 76 | #define GICD_ISENABLER_1_VALUE 0x10000000 |
| 77 | #define GICD_ISENABLER_2_VALUE 0x100 |
| 78 | #define GICD_ISENABLER_3_VALUE 0x20100 |
Pankaj Gupta | b9508bf | 2020-12-09 14:02:39 +0530 | [diff] [blame] | 79 | #define GICR_WAKER_SLEEP_BIT 0x2 |
| 80 | #define GICR_WAKER_ASLEEP (1 << 2 | 1 << 1) |
| 81 | |
| 82 | #define ICC_SRE_EL3_SRE 0x1 |
| 83 | #define ICC_IGRPEN0_EL1_EN 0x1 |
| 84 | #define ICC_CTLR_EL3_CBPR_EL1S 0x1 |
| 85 | #define ICC_CTLR_EL3_RM 0x20 |
| 86 | #define ICC_CTLR_EL3_EOIMODE_EL3 0x4 |
| 87 | #define ICC_CTLR_EL3_PMHE 0x40 |
| 88 | #define ICC_PMR_EL1_P_FILTER 0xFF |
| 89 | #define ICC_IAR0_EL1_SGI15 0xF |
| 90 | #define ICC_SGI0R_EL1_INTID 0x0F000000 |
| 91 | #define ICC_IAR0_INTID_SPI_89 0x59 |
| 92 | |
| 93 | #define ICC_IGRPEN1_EL1 S3_0_C12_C12_7 |
| 94 | #define ICC_PMR_EL1 S3_0_C4_C6_0 |
| 95 | #define ICC_SRE_EL3 S3_6_C12_C12_5 |
| 96 | #define ICC_CTLR_EL3 S3_6_C12_C12_4 |
| 97 | #define ICC_SRE_EL2 S3_4_C12_C9_5 |
| 98 | #define ICC_CTLR_EL1 S3_0_C12_C12_4 |
| 99 | |
| 100 | #ifndef __ASSEMBLER__ |
| 101 | |
| 102 | /* GIC common API's */ |
| 103 | typedef unsigned int (*my_core_pos_fn)(void); |
| 104 | |
| 105 | void plat_ls_gic_driver_init(const uintptr_t nxp_gicd_addr, |
| 106 | const uintptr_t nxp_gicr_addr, |
| 107 | uint8_t plat_core_count, |
| 108 | interrupt_prop_t *ls_interrupt_props, |
| 109 | uint8_t ls_interrupt_prop_count, |
| 110 | uintptr_t *target_mask_array, |
| 111 | mpidr_hash_fn mpidr_to_core_pos); |
| 112 | //void plat_ls_gic_driver_init(void); |
| 113 | void plat_ls_gic_init(void); |
| 114 | void plat_ls_gic_cpuif_enable(void); |
| 115 | void plat_ls_gic_cpuif_disable(void); |
| 116 | void plat_ls_gic_redistif_on(void); |
| 117 | void plat_ls_gic_redistif_off(void); |
| 118 | void plat_gic_pcpu_init(void); |
| 119 | #endif |
| 120 | |
| 121 | #endif /* PLAT_GICV3_H */ |