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git01.mediatek.com / filogic / atf / 62a84ed0f90f2d8b52115d8a82ce2b21f3c63f63 / . / include / lib / cpus / aarch64 / cortex_a53.h
blob: 4b7d238c9bb72e28dc8914c6f6f02601b7ef95b2 [file] [log] [blame]
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]1/*
Varun Wadekar1384a162017-06-05 14:54:46 -0700[diff] [blame]2 * Copyright (c) 2014-2017, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]7#ifndef CORTEX_A53_H
8#define CORTEX_A53_H
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]9
Soby Mathew8e2f2872014-08-14 12:49:05 +0100[diff] [blame]10/* Cortex-A53 midr for revision 0 */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700[diff] [blame]11#define CORTEX_A53_MIDR U(0x410FD030)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]12
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]13/* Retention timer tick definitions */
Varun Wadekarc6a11f62017-05-25 18:04:48 -0700[diff] [blame]14#define RETENTION_ENTRY_TICKS_2 U(0x1)
15#define RETENTION_ENTRY_TICKS_8 U(0x2)
16#define RETENTION_ENTRY_TICKS_32 U(0x3)
17#define RETENTION_ENTRY_TICKS_64 U(0x4)
18#define RETENTION_ENTRY_TICKS_128 U(0x5)
19#define RETENTION_ENTRY_TICKS_256 U(0x6)
20#define RETENTION_ENTRY_TICKS_512 U(0x7)
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]21
Soby Mathew8e2f2872014-08-14 12:49:05 +0100[diff] [blame]22/*******************************************************************************
23 * CPU Extended Control register specific definitions.
24 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]25#define CORTEX_A53_ECTLR_EL1 S3_1_C15_C2_1
Soby Mathew38b4bc92014-08-14 13:36:41 +0100[diff] [blame]26
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]27#define CORTEX_A53_ECTLR_SMP_BIT (U(1) << 6)
Achin Gupta4f6ad662013-10-25 09:08:21 +0100[diff] [blame]28
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]29#define CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT U(0)
30#define CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_CPU_RET_CTRL_SHIFT)
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]31
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]32#define CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT U(3)
33#define CORTEX_A53_ECTLR_FPU_RET_CTRL_MASK (U(0x7) << CORTEX_A53_ECTLR_FPU_RET_CTRL_SHIFT)
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]34
developer4fceaca2015-07-29 20:55:31 +0800[diff] [blame]35/*******************************************************************************
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]36 * CPU Memory Error Syndrome register specific definitions.
37 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]38#define CORTEX_A53_MERRSR_EL1 S3_1_C15_C2_2
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]39
40/*******************************************************************************
developer4fceaca2015-07-29 20:55:31 +0800[diff] [blame]41 * CPU Auxiliary Control register specific definitions.
42 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]43#define CORTEX_A53_CPUACTLR_EL1 S3_1_C15_C2_0
developer4fceaca2015-07-29 20:55:31 +0800[diff] [blame]44
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]45#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT U(44)
46#define CORTEX_A53_CPUACTLR_EL1_ENDCCASCI (U(1) << CORTEX_A53_CPUACTLR_EL1_ENDCCASCI_SHIFT)
47#define CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT U(27)
48#define CORTEX_A53_CPUACTLR_EL1_RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_RADIS_SHIFT)
49#define CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT U(25)
50#define CORTEX_A53_CPUACTLR_EL1_L1RADIS (U(3) << CORTEX_A53_CPUACTLR_EL1_L1RADIS_SHIFT)
51#define CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT U(24)
52#define CORTEX_A53_CPUACTLR_EL1_DTAH (U(1) << CORTEX_A53_CPUACTLR_EL1_DTAH_SHIFT)
developer4fceaca2015-07-29 20:55:31 +0800[diff] [blame]53
54/*******************************************************************************
55 * L2 Auxiliary Control register specific definitions.
56 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]57#define CORTEX_A53_L2ACTLR_EL1 S3_1_C15_C0_0
developer4fceaca2015-07-29 20:55:31 +0800[diff] [blame]58
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]59#define CORTEX_A53_L2ACTLR_ENABLE_UNIQUECLEAN (U(1) << 14)
60#define CORTEX_A53_L2ACTLR_DISABLE_CLEAN_PUSH (U(1) << 3)
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]61/*******************************************************************************
62 * L2 Extended Control register specific definitions.
63 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]64#define CORTEX_A53_L2ECTLR_EL1 S3_1_C11_C0_3
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]65
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]66#define CORTEX_A53_L2ECTLR_RET_CTRL_SHIFT U(0)
67#define CORTEX_A53_L2ECTLR_RET_CTRL_MASK (U(0x7) << L2ECTLR_RET_CTRL_SHIFT)
Varun Wadekar3ce4e882015-08-21 15:52:51 +0530[diff] [blame]68
Naga Sureshkumar Relli6a72a912016-07-01 12:52:41 +0530[diff] [blame]69/*******************************************************************************
70 * L2 Memory Error Syndrome register specific definitions.
71 ******************************************************************************/
Eleanor Bonnici41b61be2017-08-09 16:42:40 +0100[diff] [blame]72#define CORTEX_A53_L2MERRSR_EL1 S3_1_C15_C2_3
73
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000[diff] [blame]74#endif /* CORTEX_A53_H */