Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1 | /* |
Hiroyuki Nakano | 82e63c8 | 2019-05-16 09:21:37 +0900 | [diff] [blame] | 2 | * Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved. |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 7 | #include <stdint.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 8 | |
| 9 | #include <common/debug.h> |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 10 | |
| 11 | #include "boot_init_dram_regdef_e3.h" |
| 12 | #include "ddr_init_e3.h" |
| 13 | |
| 14 | #include "../dram_sub_func.h" |
| 15 | |
| 16 | /* rev.0.04 add variables */ |
| 17 | /******************************************************************************* |
| 18 | * variables |
| 19 | ******************************************************************************/ |
| 20 | uint32_t ddrBackup; |
| 21 | |
| 22 | /* rev.0.03 add Prototypes */ |
| 23 | /******************************************************************************* |
| 24 | * Prototypes |
| 25 | ******************************************************************************/ |
| 26 | /* static uint32_t init_ddr(void); rev.0.04 */ |
| 27 | /* static uint32_t recovery_from_backup_mode(void); rev.0.04 */ |
| 28 | /* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */ |
| 29 | |
| 30 | /* rev.0.03 add Comment */ |
| 31 | /******************************************************************************* |
| 32 | * register write/read function |
| 33 | ******************************************************************************/ |
| 34 | static void WriteReg_32(uint32_t a, uint32_t v) |
| 35 | { |
| 36 | (*(volatile uint32_t*)(uintptr_t)a) = v; |
| 37 | } /* WriteReg_32 */ |
| 38 | |
| 39 | static uint32_t ReadReg_32(uint32_t a) |
| 40 | { |
| 41 | uint32_t w = (*(volatile uint32_t*)(uintptr_t)a); |
| 42 | return w; |
| 43 | } /* ReadReg_32 */ |
| 44 | |
| 45 | /* rev.0.04 add Comment */ |
| 46 | /******************************************************************************* |
| 47 | * Initialize ddr |
| 48 | ******************************************************************************/ |
| 49 | uint32_t init_ddr(void) |
| 50 | { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 51 | uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; |
| 52 | uint32_t ddr_md; |
| 53 | |
| 54 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 55 | uint32_t RegVal, j; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 56 | uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; |
| 57 | uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 58 | uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 59 | /* rev.0.10 */ |
| 60 | uint32_t pdr_ctl; |
| 61 | /* rev.0.11 */ |
| 62 | uint32_t byp_ctl; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 63 | |
| 64 | /* rev.0.08 */ |
| 65 | if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { |
| 66 | pdqsr_ctl = 1; |
| 67 | lcdl_ctl = 1; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 68 | pdr_ctl = 1; /* rev.0.10 */ |
| 69 | byp_ctl = 1; /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 70 | } else { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 71 | pdqsr_ctl = 0; |
| 72 | lcdl_ctl = 0; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 73 | pdr_ctl = 0; /* rev.0.10 */ |
| 74 | byp_ctl = 0; /* rev.0.11 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 75 | } |
| 76 | |
| 77 | /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 78 | ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 79 | |
| 80 | /* 1584Mbps setting */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 81 | if (ddr_md == 0) { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 82 | /* CPG setting ===============================================*/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 83 | WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); |
| 84 | WriteReg_32(CPG_CPGWPCR, 0xA5A50000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 85 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 86 | WriteReg_32(CPG_SRCR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 87 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 88 | WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ |
| 89 | while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 90 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 91 | WriteReg_32(CPG_SRSTCLR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 92 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 93 | WriteReg_32(CPG_CPGWPCR, 0xA5A50001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 94 | |
| 95 | /* CPG setting ===============================================*/ |
| 96 | } /* ddr_md */ |
| 97 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 98 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 99 | WriteReg_32(DBSC_E3_DBKIND, 0x00000007); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 100 | |
| 101 | #if RCAR_DRAM_DDR3L_MEMCONF == 0 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 102 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 103 | #else |
Hiroyuki Nakano | 82e63c8 | 2019-05-16 09:21:37 +0900 | [diff] [blame] | 104 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 105 | #endif |
| 106 | |
| 107 | #if RCAR_DRAM_DDR3L_MEMDUAL == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 108 | RegVal_R2 = (ReadReg_32(0xE6790614)); |
| 109 | WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 110 | #endif |
| 111 | |
| 112 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 113 | WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 114 | |
| 115 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 116 | if (ddr_md == 0) { /* 1584Mbps */ |
| 117 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); |
| 118 | WriteReg_32(DBSC_E3_DBTR1, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 119 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 120 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); |
| 121 | WriteReg_32(DBSC_E3_DBTR1, 0x00000009); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 122 | } /* ddr_md */ |
| 123 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 124 | WriteReg_32(DBSC_E3_DBTR2, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 125 | |
| 126 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 127 | if (ddr_md == 0) { /* 1584Mbps */ |
| 128 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); |
| 129 | WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); |
| 130 | WriteReg_32(DBSC_E3_DBTR5, 0x00000027); |
| 131 | WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 132 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 133 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); |
| 134 | WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); |
| 135 | WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); |
| 136 | WriteReg_32(DBSC_E3_DBTR6, 0x00000020); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 137 | } /* ddr_md */ |
| 138 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 139 | WriteReg_32(DBSC_E3_DBTR7, 0x00060006); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 140 | |
| 141 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 142 | if (ddr_md == 0) { /* 1584Mbps */ |
| 143 | WriteReg_32(DBSC_E3_DBTR8, 0x00000020); |
| 144 | WriteReg_32(DBSC_E3_DBTR9, 0x00000006); |
| 145 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); |
| 146 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); |
| 147 | WriteReg_32(DBSC_E3_DBTR12, 0x00120012); |
| 148 | WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); |
| 149 | WriteReg_32(DBSC_E3_DBTR14, 0x00140005); |
| 150 | WriteReg_32(DBSC_E3_DBTR15, 0x00050004); |
| 151 | WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); |
| 152 | WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 153 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 154 | WriteReg_32(DBSC_E3_DBTR8, 0x00000021); |
| 155 | WriteReg_32(DBSC_E3_DBTR9, 0x00000007); |
| 156 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); |
| 157 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); |
| 158 | WriteReg_32(DBSC_E3_DBTR12, 0x00140014); |
| 159 | WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); |
| 160 | WriteReg_32(DBSC_E3_DBTR14, 0x00170006); |
| 161 | WriteReg_32(DBSC_E3_DBTR15, 0x00060005); |
| 162 | WriteReg_32(DBSC_E3_DBTR16, 0x09210507); |
| 163 | WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 164 | } /* ddr_md */ |
| 165 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 166 | WriteReg_32(DBSC_E3_DBTR18, 0x00000200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 167 | |
| 168 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 169 | if (ddr_md == 0) { /* 1584Mbps */ |
| 170 | WriteReg_32(DBSC_E3_DBTR19, 0x01000040); |
| 171 | WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 172 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 173 | WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); |
| 174 | WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 175 | } /* ddr_md */ |
| 176 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 177 | WriteReg_32(DBSC_E3_DBTR21, 0x00040004); |
| 178 | WriteReg_32(DBSC_E3_DBBL, 0x00000000); |
| 179 | WriteReg_32(DBSC_E3_DBODT0, 0x00000001); |
| 180 | WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); |
| 181 | WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); |
| 182 | WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); |
| 183 | WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); |
| 184 | WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 185 | |
| 186 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 187 | if (ddr_md == 0) { /* 1584Mbps */ |
| 188 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); |
| 189 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 190 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 191 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); |
| 192 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 193 | } /* ddr_md */ |
| 194 | |
| 195 | /* rev.0.03 add Comment */ |
| 196 | /**************************************************************************** |
| 197 | * Initial_Step0( INITBYP ) |
| 198 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 199 | WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); |
| 200 | WriteReg_32(DBSC_E3_DBCMD, 0x01840001); |
| 201 | WriteReg_32(DBSC_E3_DBCMD, 0x08840000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 202 | NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 203 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 204 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); |
| 205 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 206 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 207 | |
| 208 | /* rev.0.03 add Comment */ |
| 209 | /**************************************************************************** |
| 210 | * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training ) |
| 211 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 212 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); |
| 213 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); |
| 214 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 215 | |
| 216 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 217 | if (ddr_md == 0) { /* 1584Mbps */ |
| 218 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058904); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 219 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 220 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A04); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 221 | } /* ddr_md */ |
| 222 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 223 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); |
| 224 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 225 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); |
| 226 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); |
| 227 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); |
| 228 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 229 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 230 | |
| 231 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 232 | if (ddr_md == 0) { /* 1584Mbps */ |
| 233 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 234 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 235 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 236 | } /* ddr_md */ |
| 237 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 238 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 239 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); |
| 240 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 241 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); |
| 242 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 243 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 244 | |
| 245 | /* rev.0.03 add Comment */ |
| 246 | /**************************************************************************** |
| 247 | * Initial_Step2( DRAMRST/DRAMINT training ) |
| 248 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 249 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 250 | |
| 251 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 252 | if (ddr_md == 0) { /* 1584Mbps */ |
| 253 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 254 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 255 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 256 | } /* ddr_md */ |
| 257 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 258 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 259 | |
| 260 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 261 | if (ddr_md == 0) { /* 1584Mbps */ |
| 262 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 263 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 264 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 265 | } /* ddr_md */ |
| 266 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 267 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 268 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 269 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 270 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 271 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 272 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 273 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 274 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 275 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 276 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 277 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 278 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 279 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 280 | |
| 281 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 282 | if (ddr_md == 0) { /* 1584Mbps */ |
| 283 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 284 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 285 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 286 | } /* ddr_md */ |
| 287 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 288 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); |
| 289 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); |
| 290 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 291 | |
| 292 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 293 | if (ddr_md == 0) { /* 1584Mbps */ |
| 294 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 295 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 296 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 297 | } /* ddr_md */ |
| 298 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 299 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 300 | |
| 301 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 302 | if (ddr_md == 0) { /* 1584Mbps */ |
| 303 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 304 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 305 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 306 | } /* ddr_md */ |
| 307 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 308 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 309 | |
| 310 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 311 | if (ddr_md == 0) { /* 1584Mbps */ |
| 312 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 313 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 314 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 315 | } /* ddr_md */ |
| 316 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 317 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 318 | |
| 319 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 320 | if (ddr_md == 0) { /* 1584Mbps */ |
| 321 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 322 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 323 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 324 | } /* ddr_md */ |
| 325 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 326 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 327 | |
| 328 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 329 | if (ddr_md == 0) { /* 1584Mbps */ |
| 330 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 331 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 332 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 333 | } /* ddr_md */ |
| 334 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 335 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); |
| 336 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); |
| 337 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 338 | |
| 339 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 340 | if (ddr_md == 0) { /* 1584Mbps */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 341 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 342 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 343 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 344 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 345 | } |
| 346 | } else { /* 1856Mbps */ |
| 347 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 348 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 349 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 350 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 351 | } /* REFRESH_RATE */ |
| 352 | } /* ddr_md */ |
| 353 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 354 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 355 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); |
| 356 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); |
| 357 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); |
| 358 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); |
| 359 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); |
| 360 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 361 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 362 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 363 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); |
| 364 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 365 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); |
| 366 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 367 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); |
| 368 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 369 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); |
| 370 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 371 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); |
| 372 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 373 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); |
| 374 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 375 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); |
| 376 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 377 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); |
| 378 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 379 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); |
| 380 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 381 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); |
| 382 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 383 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); |
| 384 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 385 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); |
| 386 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 387 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 388 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 389 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010181); |
| 390 | WriteReg_32(DBSC_E3_DBCMD, 0x08840001); |
| 391 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 392 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 393 | |
| 394 | /* rev.0.03 add Comment */ |
| 395 | /**************************************************************************** |
| 396 | * Initial_Step3( WL/QSG training ) |
| 397 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 398 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 399 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010601); |
| 400 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 401 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 402 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 403 | for (i = 0; i < 4; i++) { |
| 404 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 405 | RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 406 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 407 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 408 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 409 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 410 | if (RegVal_R6 > 0) { |
| 411 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 412 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 413 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 414 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 415 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 416 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 417 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 418 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 419 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 420 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 421 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 422 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 423 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); |
| 424 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 425 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 426 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 427 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 428 | } /* RegVal_R6 */ |
| 429 | } /* for i */ |
| 430 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 431 | /* rev.0.10 move Comment */ |
| 432 | /**************************************************************************** |
| 433 | * Initial_Step4( WLADJ training ) |
| 434 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 435 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 436 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 437 | |
| 438 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 439 | if (pdqsr_ctl == 1){} else { |
| 440 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 441 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 442 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 443 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 444 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 445 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 446 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 447 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | /* PDR always off */ /* rev.0.10 */ |
| 451 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 452 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 453 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 454 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 455 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 456 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 457 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 458 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 459 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 460 | } |
| 461 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 462 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 463 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); |
| 464 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 465 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 466 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 467 | /**************************************************************************** |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 468 | * Initial_Step5(Read Data Bit Deskew) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 469 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 470 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 471 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 472 | |
| 473 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 474 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 475 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); |
| 476 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 477 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 478 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 479 | if (pdqsr_ctl == 1) { |
| 480 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 481 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 482 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 483 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 484 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 485 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 486 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 487 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 488 | } |
| 489 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 490 | /* PDR dynamic */ /* rev.0.10 */ |
| 491 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 492 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 493 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 494 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 495 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 496 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 497 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 498 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 499 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 500 | } |
| 501 | |
| 502 | /**************************************************************************** |
| 503 | * Initial_Step6(Write Data Bit Deskew) |
| 504 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 505 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 506 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); |
| 507 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 508 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 509 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 510 | /**************************************************************************** |
| 511 | * Initial_Step7(Read Data Eye Training) |
| 512 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 513 | if (pdqsr_ctl == 1) { |
| 514 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 515 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 516 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 517 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 518 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 519 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 520 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 521 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 522 | } |
| 523 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 524 | /* PDR always off */ /* rev.0.10 */ |
| 525 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 526 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 527 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 528 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 529 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 530 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 531 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 532 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 533 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 534 | } |
| 535 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 536 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 537 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); |
| 538 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 539 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 540 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 541 | if (pdqsr_ctl == 1) { |
| 542 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 543 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 544 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 545 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 546 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 547 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 548 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 549 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 550 | } |
| 551 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 552 | /* PDR dynamic */ /* rev.0.10 */ |
| 553 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 554 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 555 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 556 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 557 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 558 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 559 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 560 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 561 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 562 | } |
| 563 | |
| 564 | /**************************************************************************** |
| 565 | * Initial_Step8(Write Data Eye Training) |
| 566 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 567 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 568 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); |
| 569 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 570 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 571 | |
| 572 | /* rev.0.03 add Comment */ |
| 573 | /**************************************************************************** |
| 574 | * Initial_Step3_2( DQS Gate Training ) |
| 575 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 576 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 577 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 578 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 579 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 580 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 581 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 582 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 583 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 584 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 585 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); |
| 586 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 587 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); |
| 588 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 589 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 590 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 591 | for (i = 0; i < 4; i++) { |
| 592 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 593 | RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 594 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 595 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 596 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 597 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 598 | RegVal_R12 = (RegVal_R5 >> 0x2); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 599 | if (RegVal_R12 < RegVal_R6) { |
| 600 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 601 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 602 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 603 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 604 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 605 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 606 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 607 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 608 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 609 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 610 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 611 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 612 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); |
| 613 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 614 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 615 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 616 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 617 | } /* RegVal_R12 < RegVal_R6 */ |
| 618 | } /* for i */ |
| 619 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 620 | /* rev.0.10 move Comment */ |
| 621 | /**************************************************************************** |
| 622 | * Initial_Step5-2_7-2( Rd bit Rd eye ) |
| 623 | ***************************************************************************/ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 624 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 625 | if (pdqsr_ctl == 1){} else { |
| 626 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 627 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 628 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 629 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 630 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 631 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 632 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 633 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 634 | } |
| 635 | |
| 636 | /* PDR always off */ /* rev.0.10 */ |
| 637 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 638 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 639 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 640 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 641 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 642 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 643 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 644 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 645 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 646 | } |
| 647 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 648 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 649 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); |
| 650 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 651 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 652 | |
| 653 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 654 | if (lcdl_ctl == 1) { |
| 655 | for (i = 0; i < 4; i++) { |
| 656 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 657 | dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
| 658 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
| 659 | bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); |
| 660 | bdlcount_0c_div2 = (bdlcount_0c >> 1); |
| 661 | bdlcount_0c_div4 = (bdlcount_0c >> 2); |
| 662 | bdlcount_0c_div8 = (bdlcount_0c >> 3); |
| 663 | bdlcount_0c_div16 = (bdlcount_0c >> 4); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 664 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 665 | if (ddr_md == 0) { /* 1584Mbps */ |
| 666 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; |
| 667 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; |
| 668 | } else { /* 1856Mbps */ |
| 669 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; |
| 670 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; |
| 671 | } /* ddr_md */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 672 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 673 | if (dqsgd_0c > lcdl_judge1) { |
| 674 | if (dqsgd_0c <= lcdl_judge2) { |
| 675 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 676 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 677 | WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); |
| 678 | } else { |
| 679 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 680 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 681 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 682 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 683 | gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 684 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 685 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 686 | WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); |
| 687 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 688 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 689 | rdqsd_0c = (RegVal & 0x0000FF00) >> 8; |
| 690 | rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; |
| 691 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 692 | WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); |
| 693 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 694 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 695 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 696 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 697 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 698 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 699 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 700 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 701 | for (j = 0; j < 4; j++) { |
| 702 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 703 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 704 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 705 | } |
| 706 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 707 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 708 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 709 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 710 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 711 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 712 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 713 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 714 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 715 | for (j = 0; j < 4; j++) { |
| 716 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 717 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 718 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 719 | } |
| 720 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 721 | } |
| 722 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 723 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 724 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); |
| 725 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 726 | } |
| 727 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 728 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 729 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 730 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 731 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 732 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 733 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 734 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 735 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 736 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 737 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 738 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 739 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 740 | WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); |
| 741 | WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 742 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 743 | if (ddr_md == 0) { /* 1584Mbps */ |
| 744 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 745 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 746 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 747 | } /* ddr_md */ |
| 748 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 749 | WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); |
| 750 | WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); |
| 751 | WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); |
| 752 | WriteReg_32(DBSC_E3_DBACEN, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 753 | |
| 754 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 755 | if (pdqsr_ctl == 1) { |
| 756 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 757 | RegVal = ReadReg_32(0x40000000); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 758 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); |
| 759 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 760 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 761 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 762 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 763 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 764 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 765 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 766 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 767 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 768 | } |
| 769 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 770 | /* PDR dynamic */ /* rev.0.10 */ |
| 771 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 772 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 773 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 774 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 775 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 776 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 777 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 778 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 779 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 780 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 781 | |
| 782 | /* rev.0.03 add Comment */ |
| 783 | /**************************************************************************** |
| 784 | * Initial_Step9( Initial End ) |
| 785 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 786 | WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); |
| 787 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 788 | |
| 789 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 790 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 791 | WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); |
| 792 | WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); |
| 793 | WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); |
| 794 | WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); |
| 795 | WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); |
| 796 | WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); |
| 797 | WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); |
| 798 | WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); |
| 799 | WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); |
| 800 | WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); |
| 801 | WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); |
| 802 | WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); |
| 803 | WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); |
| 804 | WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); |
| 805 | WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); |
| 806 | WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); |
| 807 | WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); |
| 808 | WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); |
| 809 | WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); |
| 810 | WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); |
| 811 | WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); |
| 812 | WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); |
| 813 | WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); |
| 814 | WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); |
| 815 | WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); |
| 816 | WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); |
| 817 | WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); |
| 818 | WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); |
| 819 | WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); |
| 820 | WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 821 | |
| 822 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 823 | if (pdqsr_ctl == 1){} else { |
| 824 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 825 | } |
| 826 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 827 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 828 | #endif |
| 829 | |
| 830 | return 1; /* rev.0.04 Restore the return code */ |
| 831 | |
| 832 | } /* init_ddr */ |
| 833 | |
| 834 | /* rev.0.04 add function */ |
| 835 | uint32_t recovery_from_backup_mode(void) |
| 836 | { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 837 | /**************************************************************************** |
| 838 | * recovery_Step0(DBSC Setting 1) / same "init_ddr" |
| 839 | ***************************************************************************/ |
| 840 | uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i; |
| 841 | uint32_t ddr_md; |
| 842 | uint32_t err; |
| 843 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 844 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 845 | uint32_t RegVal, j; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 846 | uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16; |
| 847 | uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4]; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 848 | uint32_t pdqsr_ctl, lcdl_ctl, lcdl_judge1, lcdl_judge2; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 849 | /* rev.0.10 */ |
| 850 | uint32_t pdr_ctl; |
| 851 | /* rev.0.11 */ |
| 852 | uint32_t byp_ctl; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 853 | |
| 854 | /* rev.0.08 */ |
| 855 | if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) { |
| 856 | pdqsr_ctl = 1; |
| 857 | lcdl_ctl = 1; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 858 | pdr_ctl = 1; /* rev.0.10 */ |
| 859 | byp_ctl = 1; /* rev.0.11 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 860 | } else { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 861 | pdqsr_ctl = 0; |
| 862 | lcdl_ctl = 0; |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 863 | pdr_ctl = 0; /* rev.0.10 */ |
| 864 | byp_ctl = 0; /* rev.0.11 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 865 | } |
| 866 | |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 867 | /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 868 | ddr_md = (ReadReg_32(RST_MODEMR) >> 19) & BIT0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 869 | |
| 870 | /* 1584Mbps setting */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 871 | if (ddr_md == 0) { |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 872 | /* CPG setting ===============================================*/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 873 | WriteReg_32(CPG_CPGWPR, 0x5A5AFFFF); |
| 874 | WriteReg_32(CPG_CPGWPCR, 0xA5A50000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 875 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 876 | WriteReg_32(CPG_SRCR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 877 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 878 | WriteReg_32(0xE61500DC, 0xe2200000); /* Change to 1584Mbps */ |
| 879 | while ((BIT11 & ReadReg_32(CPG_PLLECR)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 880 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 881 | WriteReg_32(CPG_SRSTCLR4, 0x20000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 882 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 883 | WriteReg_32(CPG_CPGWPCR, 0xA5A50001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 884 | |
| 885 | /* CPG setting ===============================================*/ |
| 886 | } /* ddr_md */ |
| 887 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 888 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 889 | WriteReg_32(DBSC_E3_DBKIND, 0x00000007); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 890 | |
| 891 | #if RCAR_DRAM_DDR3L_MEMCONF == 0 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 892 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 893 | #else |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 894 | WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 895 | #endif |
| 896 | |
| 897 | /* rev.0.08 */ |
| 898 | #if RCAR_DRAM_DDR3L_MEMDUAL == 1 |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 899 | RegVal_R2 = (ReadReg_32(0xE6790614)); |
| 900 | WriteReg_32(0xE6790614, RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 901 | #endif |
| 902 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 903 | WriteReg_32(DBSC_E3_DBPHYCONF0, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 904 | |
| 905 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 906 | if (ddr_md == 0) { /* 1584Mbps */ |
| 907 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000B); |
| 908 | WriteReg_32(DBSC_E3_DBTR1, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 909 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 910 | WriteReg_32(DBSC_E3_DBTR0, 0x0000000D); |
| 911 | WriteReg_32(DBSC_E3_DBTR1, 0x00000009); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 912 | } /* ddr_md */ |
| 913 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 914 | WriteReg_32(DBSC_E3_DBTR2, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 915 | |
| 916 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 917 | if (ddr_md == 0) { /* 1584Mbps */ |
| 918 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000B); |
| 919 | WriteReg_32(DBSC_E3_DBTR4, 0x000B000B); |
| 920 | WriteReg_32(DBSC_E3_DBTR5, 0x00000027); |
| 921 | WriteReg_32(DBSC_E3_DBTR6, 0x0000001C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 922 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 923 | WriteReg_32(DBSC_E3_DBTR3, 0x0000000D); |
| 924 | WriteReg_32(DBSC_E3_DBTR4, 0x000D000D); |
| 925 | WriteReg_32(DBSC_E3_DBTR5, 0x0000002D); |
| 926 | WriteReg_32(DBSC_E3_DBTR6, 0x00000020); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 927 | } /* ddr_md */ |
| 928 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 929 | WriteReg_32(DBSC_E3_DBTR7, 0x00060006); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 930 | |
| 931 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 932 | if (ddr_md == 0) { /* 1584Mbps */ |
| 933 | WriteReg_32(DBSC_E3_DBTR8, 0x00000020); |
| 934 | WriteReg_32(DBSC_E3_DBTR9, 0x00000006); |
| 935 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000C); |
| 936 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000A); |
| 937 | WriteReg_32(DBSC_E3_DBTR12, 0x00120012); |
| 938 | WriteReg_32(DBSC_E3_DBTR13, 0x000000CE); |
| 939 | WriteReg_32(DBSC_E3_DBTR14, 0x00140005); |
| 940 | WriteReg_32(DBSC_E3_DBTR15, 0x00050004); |
| 941 | WriteReg_32(DBSC_E3_DBTR16, 0x071F0305); |
| 942 | WriteReg_32(DBSC_E3_DBTR17, 0x040C0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 943 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 944 | WriteReg_32(DBSC_E3_DBTR8, 0x00000021); |
| 945 | WriteReg_32(DBSC_E3_DBTR9, 0x00000007); |
| 946 | WriteReg_32(DBSC_E3_DBTR10, 0x0000000E); |
| 947 | WriteReg_32(DBSC_E3_DBTR11, 0x0000000C); |
| 948 | WriteReg_32(DBSC_E3_DBTR12, 0x00140014); |
| 949 | WriteReg_32(DBSC_E3_DBTR13, 0x000000F2); |
| 950 | WriteReg_32(DBSC_E3_DBTR14, 0x00170006); |
| 951 | WriteReg_32(DBSC_E3_DBTR15, 0x00060005); |
| 952 | WriteReg_32(DBSC_E3_DBTR16, 0x09210507); |
| 953 | WriteReg_32(DBSC_E3_DBTR17, 0x040E0000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 954 | } /* ddr_md */ |
| 955 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 956 | WriteReg_32(DBSC_E3_DBTR18, 0x00000200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 957 | |
| 958 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 959 | if (ddr_md == 0) { /* 1584Mbps */ |
| 960 | WriteReg_32(DBSC_E3_DBTR19, 0x01000040); |
| 961 | WriteReg_32(DBSC_E3_DBTR20, 0x020000D6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 962 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 963 | WriteReg_32(DBSC_E3_DBTR19, 0x0129004B); |
| 964 | WriteReg_32(DBSC_E3_DBTR20, 0x020000FB); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 965 | } /* ddr_md */ |
| 966 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 967 | WriteReg_32(DBSC_E3_DBTR21, 0x00040004); |
| 968 | WriteReg_32(DBSC_E3_DBBL, 0x00000000); |
| 969 | WriteReg_32(DBSC_E3_DBODT0, 0x00000001); |
| 970 | WriteReg_32(DBSC_E3_DBADJ0, 0x00000001); |
| 971 | WriteReg_32(DBSC_E3_DBSYSCONF1, 0x00000002); |
| 972 | WriteReg_32(DBSC_E3_DBDFICNT0, 0x00000010); |
| 973 | WriteReg_32(DBSC_E3_DBBCAMDIS, 0x00000001); |
| 974 | WriteReg_32(DBSC_E3_DBSCHRW1, 0x00000046); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 975 | |
| 976 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 977 | if (ddr_md == 0) { /* 1584Mbps */ |
| 978 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0D050B03); |
| 979 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0306030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 980 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 981 | WriteReg_32(DBSC_E3_SCFCTST0, 0x0C050B03); |
| 982 | WriteReg_32(DBSC_E3_SCFCTST1, 0x0305030C); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 983 | } /* ddr_md */ |
| 984 | |
| 985 | /**************************************************************************** |
| 986 | * recovery_Step1(PHY setting 1) |
| 987 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 988 | WriteReg_32(DBSC_E3_DBPDLK0, 0x0000A55A); |
| 989 | WriteReg_32(DBSC_E3_DBCMD, 0x01840001); |
| 990 | WriteReg_32(DBSC_E3_DBCMD, 0x0A840000); |
| 991 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000008); /* DDR_PLLCR */ |
| 992 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000B8000); |
| 993 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); /* DDR_PGCR1 */ |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 994 | if (byp_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 995 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 996 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 997 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0780C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 998 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 999 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000020); /* DDR_DXCCR */ |
| 1000 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00181884); |
| 1001 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000001A); /* DDR_ACIOCR0 */ |
| 1002 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x33C03C10); |
| 1003 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 1004 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1005 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1006 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000004); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1007 | |
| 1008 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1009 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1010 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 792 / 125) - 400 + 0x08B00000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1011 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1012 | WriteReg_32(DBSC_E3_DBPDRGD0, (uint32_t)(REFRESH_RATE * 928 / 125) - 400 + 0x0A300000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1013 | } /* ddr_md */ |
| 1014 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1015 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000022); |
| 1016 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x1000040B); |
| 1017 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000023); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1018 | |
| 1019 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1020 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1021 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2D9C0B66); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1022 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1023 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x35A00D77); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1024 | } /* ddr_md */ |
| 1025 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1026 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000024); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1027 | |
| 1028 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1029 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1030 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A88B400); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1031 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1032 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x2A8A2C28); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1033 | } /* ddr_md */ |
| 1034 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1035 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000025); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1036 | |
| 1037 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1038 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1039 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005200); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1040 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1041 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x30005E00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1042 | } /* ddr_md */ |
| 1043 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1044 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000026); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1045 | |
| 1046 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1047 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1048 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014A9C9); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1049 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1050 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0014CB49); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1051 | } /* ddr_md */ |
| 1052 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1053 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000027); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1054 | |
| 1055 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1056 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1057 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000D70); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1058 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1059 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000F14); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1060 | } /* ddr_md */ |
| 1061 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1062 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000028); |
| 1063 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000046); |
| 1064 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000029); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1065 | |
| 1066 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1067 | if (ddr_md == 0) { /* 1584Mbps */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1068 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1069 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000018); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1070 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1071 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000098); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1072 | } |
| 1073 | } else { /* 1856Mbps */ |
| 1074 | if (REFRESH_RATE > 3900) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1075 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000020); /* [7]SRT=0 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1076 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1077 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000000A0); /* [7]SRT=1 */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1078 | } /* REFRESH_RATE */ |
| 1079 | } /* ddr_md */ |
| 1080 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1081 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 1082 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003047); |
| 1083 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000091); |
| 1084 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 1085 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000095); |
| 1086 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BBAD); |
| 1087 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000099); |
| 1088 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0007BB6B); |
| 1089 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); /* DDR_DSGCR */ |
| 1090 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024641E); |
| 1091 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1092 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1093 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1094 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1095 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x40010000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1096 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1097 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1098 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1099 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1100 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ |
| 1101 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); |
| 1102 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ |
| 1103 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC4285FBF); |
| 1104 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ |
| 1105 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC2C59AB5); |
| 1106 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1107 | |
| 1108 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1109 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1110 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1111 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1112 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1113 | } /* ddr_md */ |
| 1114 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1115 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1116 | |
| 1117 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1118 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1119 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1120 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1121 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1122 | } /* ddr_md */ |
| 1123 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1124 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1125 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00050001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1126 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1127 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1128 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1129 | |
| 1130 | /* ddr backupmode end */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1131 | if (ddrBackup) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1132 | NOTICE("BL2: [WARM_BOOT]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1133 | } else { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1134 | NOTICE("BL2: [COLD_BOOT]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1135 | } /* ddrBackup */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1136 | err = rcar_dram_update_boot_status(ddrBackup); |
| 1137 | if (err) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1138 | NOTICE("BL2: [BOOT_STATUS_UPDATE_ERROR]\n"); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1139 | return INITDRAM_ERR_I; |
| 1140 | } /* err */ |
| 1141 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1142 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000092); /* DDR_ZQ0DR */ |
| 1143 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); |
| 1144 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000096); /* DDR_ZQ1DR */ |
| 1145 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04285FBF); |
| 1146 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000009A); /* DDR_ZQ2DR */ |
| 1147 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x02C59AB5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1148 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1149 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1150 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x08000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1151 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1152 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1153 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000003); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1154 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1155 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1156 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1157 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1158 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1159 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x80010000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1160 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1161 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1162 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1163 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1164 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1165 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010073); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1166 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1167 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1168 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1169 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1170 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1171 | |
| 1172 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1173 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1174 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1175 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1176 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0C058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1177 | } /* ddr_md */ |
| 1178 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1179 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000090); /* DDR_ZQCR */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1180 | |
| 1181 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1182 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1183 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058900); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1184 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1185 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x04058A00); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1186 | } /* ddr_md */ |
| 1187 | |
| 1188 | /* rev0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1189 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000000C); |
| 1190 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x18000040); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1191 | |
| 1192 | /**************************************************************************** |
| 1193 | * recovery_Step2(PHY setting 2) |
| 1194 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1195 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1196 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1197 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1198 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A7); |
| 1199 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1200 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A8); |
| 1201 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1202 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A9); |
| 1203 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1204 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C7); |
| 1205 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1206 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C8); |
| 1207 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1208 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C9); |
| 1209 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1210 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E7); |
| 1211 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1212 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E8); |
| 1213 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1214 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E9); |
| 1215 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
| 1216 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000107); |
| 1217 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1218 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000108); |
| 1219 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0D0D0D0D); |
| 1220 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000109); |
| 1221 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x000D0D0D); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1222 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1223 | WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000 / REFRESH_RATE) + 0x01000000); |
| 1224 | WriteReg_32(DBSC_E3_DBBUS0CNF1, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1225 | |
| 1226 | /* Select setting value in bps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1227 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1228 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 99 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1229 | } else { /* 1856Mbps */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1230 | WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE * 116 / 125) + 0x00080000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1231 | } /* ddr_md */ |
| 1232 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1233 | WriteReg_32(DBSC_E3_DBRFCNF2, 0x00010000); |
| 1234 | WriteReg_32(DBSC_E3_DBRFEN, 0x00000001); |
| 1235 | WriteReg_32(DBSC_E3_DBCMD, 0x0A840001); |
| 1236 | while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1237 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1238 | WriteReg_32(DBSC_E3_DBCMD, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1239 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1240 | WriteReg_32(DBSC_E3_DBCMD, 0x04840010); |
| 1241 | while ((BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1242 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1243 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1244 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1245 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1246 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); /* DDR_PIR */ |
| 1247 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010701); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1248 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1249 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); /* DDR_PGSR0 */ |
| 1250 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1251 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1252 | for (i = 0; i < 4; i++) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1253 | { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1254 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1255 | RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1256 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1257 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1258 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1259 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1260 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1261 | if (RegVal_R6 > 0) { |
| 1262 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1263 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1264 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1265 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 1266 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1267 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1268 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1269 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R6); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1270 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1271 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1272 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1273 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1274 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | RegVal_R7); |
| 1275 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1276 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1277 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1278 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1279 | } /* RegVal_R6 */ |
| 1280 | } /* for i */ |
| 1281 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1282 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 1283 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00C0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1284 | |
| 1285 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1286 | if (pdqsr_ctl == 1){} else { |
| 1287 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1288 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1289 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1290 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1291 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1292 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1293 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1294 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1295 | } |
| 1296 | |
| 1297 | /* PDR always off */ /* rev.0.10 */ |
| 1298 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1299 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1300 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1301 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1302 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1303 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1304 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1305 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1306 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1307 | } |
| 1308 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1309 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1310 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010801); |
| 1311 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1312 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1313 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1314 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000005); |
| 1315 | WriteReg_32(DBSC_E3_DBPDRGD0, 0xC1AA00D8); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1316 | |
| 1317 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1318 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1319 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00011001); |
| 1320 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1321 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1322 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1323 | if (pdqsr_ctl == 1) { |
| 1324 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1325 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1326 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1327 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1328 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1329 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1330 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1331 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1332 | } |
| 1333 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1334 | /* PDR dynamic */ /* rev.0.10 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1335 | if (pdr_ctl == 1) { |
| 1336 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1337 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1338 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1339 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1340 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1341 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1342 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1343 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1344 | } |
| 1345 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1346 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1347 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00012001); |
| 1348 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1349 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1350 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1351 | if (pdqsr_ctl == 1) { |
| 1352 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1353 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1354 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1355 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1356 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1357 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1358 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1359 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1360 | } |
| 1361 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1362 | /* PDR always off */ /* rev.0.10 */ |
| 1363 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1364 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1365 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1366 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1367 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1368 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1369 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1370 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1371 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1372 | } |
| 1373 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1374 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1375 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00014001); |
| 1376 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1377 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1378 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1379 | if (pdqsr_ctl == 1) { |
| 1380 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1381 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1382 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1383 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1384 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1385 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1386 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1387 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1388 | } |
| 1389 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1390 | /* PDR dynamic */ /* rev.0.10 */ |
| 1391 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1392 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1393 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1394 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1395 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1396 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1397 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1398 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1399 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1400 | } |
| 1401 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1402 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1403 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00018001); |
| 1404 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1405 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1406 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1407 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1408 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1409 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1410 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1411 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1412 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1413 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1414 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C000285); |
| 1415 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x0000002C); |
| 1416 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x81003087); |
| 1417 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1418 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00010401); |
| 1419 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1420 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1421 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1422 | for (i = 0; i < 4; i++) { |
| 1423 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1424 | RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1425 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B4 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1426 | RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1427 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B3 + i * 0x20); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1428 | RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1429 | RegVal_R12 = (RegVal_R5 >> 0x2); |
| 1430 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1431 | if (RegVal_R12 < RegVal_R6) { |
| 1432 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1433 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1434 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1435 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007)); |
| 1436 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1437 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1438 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1439 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1440 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1441 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1442 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1443 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1444 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | (RegVal_R7 & 0x00000007)); |
| 1445 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1446 | RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1447 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1448 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF)); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1449 | } /* RegVal_R12 < RegVal_R6 */ |
| 1450 | } /* for i */ |
| 1451 | |
| 1452 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1453 | if (pdqsr_ctl == 1){} else { |
| 1454 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1455 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1456 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1457 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1458 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1459 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1460 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1461 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1462 | } |
| 1463 | |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1464 | /* PDR always off */ /* rev.0.10 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1465 | if (pdr_ctl == 1) { |
| 1466 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1467 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1468 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1469 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1470 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1471 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
| 1472 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1473 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000008); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1474 | } |
| 1475 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1476 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000001); |
| 1477 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00015001); |
| 1478 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000006); |
| 1479 | while ((BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1480 | |
| 1481 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1482 | if (lcdl_ctl == 1) { |
| 1483 | for (i = 0; i < 4; i++) { |
| 1484 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1485 | dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF); |
| 1486 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B1 + i * 0x20); |
| 1487 | bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8); |
| 1488 | bdlcount_0c_div2 = (bdlcount_0c >> 1); |
| 1489 | bdlcount_0c_div4 = (bdlcount_0c >> 2); |
| 1490 | bdlcount_0c_div8 = (bdlcount_0c >> 3); |
| 1491 | bdlcount_0c_div16 = (bdlcount_0c >> 4); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1492 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1493 | if (ddr_md == 0) { /* 1584Mbps */ |
| 1494 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8; |
| 1495 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16; |
| 1496 | } else { /* 1856Mbps */ |
| 1497 | lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4; |
| 1498 | lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4; |
| 1499 | } /* ddr_md */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1500 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1501 | if (dqsgd_0c > lcdl_judge1) { |
| 1502 | if (dqsgd_0c <= lcdl_judge2) { |
| 1503 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1504 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1505 | WriteReg_32(DBSC_E3_DBPDRGD0, ((dqsgd_0c - bdlcount_0c_div8) | RegVal)); |
| 1506 | } else { |
| 1507 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20); |
| 1508 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00); |
| 1509 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1510 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1511 | gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007); |
| 1512 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20); |
| 1513 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8); |
| 1514 | WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal | (gatesl_0c + 1))); |
| 1515 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 1516 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1517 | rdqsd_0c = (RegVal & 0x0000FF00) >> 8; |
| 1518 | rdqsnd_0c = (RegVal & 0x00FF0000) >> 16; |
| 1519 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20); |
| 1520 | WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF) | ((rdqsd_0c + bdlcount_0c_div4) << 8) | ((rdqsnd_0c + bdlcount_0c_div4) << 16))); |
| 1521 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 1522 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1523 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 1524 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 1525 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 1526 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 1527 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20); |
| 1528 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 1529 | for (j = 0; j < 4; j++) { |
| 1530 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 1531 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 1532 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 1533 | } |
| 1534 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1535 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 1536 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0)); |
| 1537 | rbd_0c[0] = (RegVal) &0x0000001f; |
| 1538 | rbd_0c[1] = (RegVal >> 8) & 0x0000001f; |
| 1539 | rbd_0c[2] = (RegVal >> 16) & 0x0000001f; |
| 1540 | rbd_0c[3] = (RegVal >> 24) & 0x0000001f; |
| 1541 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20); |
| 1542 | RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0); |
| 1543 | for (j = 0; j < 4; j++) { |
| 1544 | rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4); |
| 1545 | if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F; |
| 1546 | RegVal = RegVal | (rbd_0c[j] << 8 * j); |
| 1547 | } |
| 1548 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1549 | } |
| 1550 | } |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1551 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1552 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000002); |
| 1553 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x07D81E37); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1554 | } |
| 1555 | |
| 1556 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1557 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000003); |
| 1558 | if (byp_ctl == 1) { |
| 1559 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C720); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1560 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1561 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0380C700); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1562 | } |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1563 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000007); |
| 1564 | while ((BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0); |
| 1565 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000021); |
| 1566 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x0024643E); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1567 | |
| 1568 | /**************************************************************************** |
| 1569 | * recovery_Step3(DBSC Setting 2) |
| 1570 | ***************************************************************************/ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1571 | WriteReg_32(DBSC_E3_DBDFICUPDCNF, 0x40100001); |
| 1572 | WriteReg_32(DBSC_E3_DBACEN, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1573 | |
| 1574 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1575 | if (pdqsr_ctl == 1) { |
| 1576 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1577 | RegVal = ReadReg_32(0x40000000); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1578 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000000); |
| 1579 | WriteReg_32(DBSC_E3_DBPDRGD0, RegVal); |
| 1580 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A0); |
| 1581 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1582 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C0); |
| 1583 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1584 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E0); |
| 1585 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
| 1586 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000100); |
| 1587 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x7C0002C5); |
Marek Vasut | 432d767 | 2018-12-12 18:06:39 +0100 | [diff] [blame] | 1588 | } |
| 1589 | |
| 1590 | /* PDR dynamic */ /* rev.0.10 */ |
| 1591 | if (pdr_ctl == 1) { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1592 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000A3); |
| 1593 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1594 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000C3); |
| 1595 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1596 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000E3); |
| 1597 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
| 1598 | WriteReg_32(DBSC_E3_DBPDRGA0, 0x00000103); |
| 1599 | WriteReg_32(DBSC_E3_DBPDRGD0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1600 | } |
| 1601 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1602 | WriteReg_32(DBSC_E3_DBPDLK0, 0x00000000); |
| 1603 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1604 | |
| 1605 | #ifdef ddr_qos_init_setting /* only for non qos_init */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1606 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00001234); |
| 1607 | WriteReg_32(DBSC_E3_DBCAM0CNF1, 0x00043218); |
| 1608 | WriteReg_32(DBSC_E3_DBCAM0CNF2, 0x000000F4); |
| 1609 | WriteReg_32(DBSC_E3_DBSCHCNT0, 0x000f0037); |
| 1610 | WriteReg_32(DBSC_E3_DBSCHSZ0, 0x00000001); |
| 1611 | WriteReg_32(DBSC_E3_DBSCHRW0, 0x22421111); |
| 1612 | WriteReg_32(DBSC_E3_SCFCTST2, 0x012F1123); |
| 1613 | WriteReg_32(DBSC_E3_DBSCHQOS00, 0x00000F00); |
| 1614 | WriteReg_32(DBSC_E3_DBSCHQOS01, 0x00000B00); |
| 1615 | WriteReg_32(DBSC_E3_DBSCHQOS02, 0x00000000); |
| 1616 | WriteReg_32(DBSC_E3_DBSCHQOS03, 0x00000000); |
| 1617 | WriteReg_32(DBSC_E3_DBSCHQOS40, 0x00000300); |
| 1618 | WriteReg_32(DBSC_E3_DBSCHQOS41, 0x000002F0); |
| 1619 | WriteReg_32(DBSC_E3_DBSCHQOS42, 0x00000200); |
| 1620 | WriteReg_32(DBSC_E3_DBSCHQOS43, 0x00000100); |
| 1621 | WriteReg_32(DBSC_E3_DBSCHQOS90, 0x00000100); |
| 1622 | WriteReg_32(DBSC_E3_DBSCHQOS91, 0x000000F0); |
| 1623 | WriteReg_32(DBSC_E3_DBSCHQOS92, 0x000000A0); |
| 1624 | WriteReg_32(DBSC_E3_DBSCHQOS93, 0x00000040); |
| 1625 | WriteReg_32(DBSC_E3_DBSCHQOS130, 0x00000100); |
| 1626 | WriteReg_32(DBSC_E3_DBSCHQOS131, 0x000000F0); |
| 1627 | WriteReg_32(DBSC_E3_DBSCHQOS132, 0x000000A0); |
| 1628 | WriteReg_32(DBSC_E3_DBSCHQOS133, 0x00000040); |
| 1629 | WriteReg_32(DBSC_E3_DBSCHQOS140, 0x000000C0); |
| 1630 | WriteReg_32(DBSC_E3_DBSCHQOS141, 0x000000B0); |
| 1631 | WriteReg_32(DBSC_E3_DBSCHQOS142, 0x00000080); |
| 1632 | WriteReg_32(DBSC_E3_DBSCHQOS143, 0x00000040); |
| 1633 | WriteReg_32(DBSC_E3_DBSCHQOS150, 0x00000040); |
| 1634 | WriteReg_32(DBSC_E3_DBSCHQOS151, 0x00000030); |
| 1635 | WriteReg_32(DBSC_E3_DBSCHQOS152, 0x00000020); |
| 1636 | WriteReg_32(DBSC_E3_DBSCHQOS153, 0x00000010); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1637 | |
| 1638 | /* rev.0.08 */ |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1639 | if (pdqsr_ctl == 1){} else { |
| 1640 | WriteReg_32(0xE67F0018, 0x00000001); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1641 | } |
| 1642 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1643 | WriteReg_32(DBSC_E3_DBSYSCNT0, 0x00000000); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1644 | #endif |
| 1645 | |
| 1646 | return 1; |
| 1647 | |
| 1648 | } /* recovery_from_backup_mode */ |
| 1649 | |
| 1650 | /******************************************************************************* |
| 1651 | * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps |
| 1652 | ******************************************************************************/ |
| 1653 | |
| 1654 | /******************************************************************************* |
| 1655 | * DDR Initialize entry for IPL |
| 1656 | ******************************************************************************/ |
ldts | 0a596b4 | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 1657 | int32_t rcar_dram_init(void) |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1658 | { |
| 1659 | uint32_t dataL; |
| 1660 | uint32_t failcount; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1661 | uint32_t md = 0; |
| 1662 | uint32_t ddr = 0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1663 | |
| 1664 | md = *((volatile uint32_t*)RST_MODEMR); |
| 1665 | ddr = (md & 0x00080000) >> 19; |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1666 | if (ddr == 0x0) { |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1667 | NOTICE("BL2: DDR1584(%s)\n", RCAR_E3_DDR_VERSION); |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1668 | } else if(ddr == 0x1){ |
Marek Vasut | 5651989 | 2019-01-21 23:11:33 +0100 | [diff] [blame] | 1669 | NOTICE("BL2: DDR1856(%s)\n", RCAR_E3_DDR_VERSION); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1670 | } /* ddr */ |
| 1671 | |
ldts | 0a596b4 | 2018-11-06 10:17:12 +0100 | [diff] [blame] | 1672 | rcar_dram_get_boot_status(&ddrBackup); |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1673 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1674 | if (ddrBackup == DRAM_BOOT_STATUS_WARM) { |
| 1675 | dataL = recovery_from_backup_mode(); /* WARM boot */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1676 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1677 | dataL = init_ddr(); /* COLD boot */ |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1678 | } /* ddrBackup */ |
| 1679 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1680 | if (dataL == 1) { |
| 1681 | failcount = 0; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1682 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1683 | failcount = 1; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1684 | } /* dataL */ |
| 1685 | |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1686 | if (failcount == 0) { |
| 1687 | return INITDRAM_OK; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1688 | } else { |
Marek Vasut | 1ddb3bf | 2018-12-16 19:28:59 +0100 | [diff] [blame] | 1689 | return INITDRAM_NG; |
Jorge Ramirez-Ortiz | 47503d2 | 2018-09-23 09:36:52 +0200 | [diff] [blame] | 1690 | } /* failcount */ |
| 1691 | } /* InitDram */ |
| 1692 | |
| 1693 | /******************************************************************************* |
| 1694 | * END |
| 1695 | ******************************************************************************/ |