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git01.mediatek.com / filogic / atf / 432d7670a6f9c759a92d7b1a5e3da3f645482a8c / . / drivers / staging / renesas / rcar / ddr / ddr_a / ddr_init_e3.c
blob: 076fafbd928f1a69ee1725a955990065151b03d2 [file] [log] [blame]
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1/*
2 * Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]7#include <stdint.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000[diff] [blame]8
9#include <common/debug.h>
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]10
11#include "boot_init_dram_regdef_e3.h"
12#include "ddr_init_e3.h"
13
14#include "../dram_sub_func.h"
15
16/* rev.0.04 add variables */
17/*******************************************************************************
18 * variables
19 ******************************************************************************/
20uint32_t ddrBackup;
21
22/* rev.0.03 add Prototypes */
23/*******************************************************************************
24 * Prototypes
25 ******************************************************************************/
26/* static uint32_t init_ddr(void); rev.0.04 */
27/* static uint32_t recovery_from_backup_mode(void); rev.0.04 */
28/* int32_t dram_update_boot_status(uint32_t status); rev.0.04 */
29
30/* rev.0.03 add Comment */
31/*******************************************************************************
32 * register write/read function
33 ******************************************************************************/
34static void WriteReg_32(uint32_t a, uint32_t v)
35{
36 (*(volatile uint32_t*)(uintptr_t)a) = v;
37} /* WriteReg_32 */
38
39static uint32_t ReadReg_32(uint32_t a)
40{
41 uint32_t w = (*(volatile uint32_t*)(uintptr_t)a);
42 return w;
43} /* ReadReg_32 */
44
45/* rev.0.04 add Comment */
46/*******************************************************************************
47 * Initialize ddr
48 ******************************************************************************/
49uint32_t init_ddr(void)
50{
51
52 uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
53 uint32_t ddr_md;
54
55/* rev.0.08 */
56 uint32_t RegVal,j;
57 uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
58 uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
59 uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]60/* rev.0.10 */
61 uint32_t pdr_ctl;
62/* rev.0.11 */
63 uint32_t byp_ctl;
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]64
65/* rev.0.08 */
66 if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
67 pdqsr_ctl = 1;
68 lcdl_ctl = 1;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]69 pdr_ctl = 1; /* rev.0.10 */
70 byp_ctl = 1; /* rev.0.11 */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]71 }else {
72 pdqsr_ctl = 0;
73 lcdl_ctl = 0;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]74 pdr_ctl = 0; /* rev.0.10 */
75 byp_ctl = 0; /* rev.0.11 */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]76 }
77
78 /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
79 ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
80
81 /* 1584Mbps setting */
82 if (ddr_md==0){
83 /* CPG setting ===============================================*/
84 WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
85 WriteReg_32(CPG_CPGWPCR,0xA5A50000);
86
87 WriteReg_32(CPG_SRCR4,0x20000000);
88
89 WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
90 while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
91
92 WriteReg_32(CPG_SRSTCLR4,0x20000000);
93
94 WriteReg_32(CPG_CPGWPCR,0xA5A50001);
95
96 /* CPG setting ===============================================*/
97 } /* ddr_md */
98
99 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
100 WriteReg_32(DBSC_E3_DBKIND,0x00000007);
101
102
103#if RCAR_DRAM_DDR3L_MEMCONF == 0
104 WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02); /* 1GB */
105#elif RCAR_DRAM_DDR3L_MEMCONF == 1
106 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB(default) */
107#elif RCAR_DRAM_DDR3L_MEMCONF == 2
108 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02); /* 4GB */
109#else
110 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02); /* 2GB */
111#endif
112
113#if RCAR_DRAM_DDR3L_MEMDUAL == 1
114 RegVal_R2 = (ReadReg_32(0xE6790614));
115 WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
116#endif
117
118
119
120 WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
121
122 /* Select setting value in bps */
123 if (ddr_md==0){ /* 1584Mbps */
124 WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
125 WriteReg_32(DBSC_E3_DBTR1,0x00000008);
126 } else { /* 1856Mbps */
127 WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
128 WriteReg_32(DBSC_E3_DBTR1,0x00000009);
129 } /* ddr_md */
130
131 WriteReg_32(DBSC_E3_DBTR2,0x00000000);
132
133 /* Select setting value in bps */
134 if (ddr_md==0){ /* 1584Mbps */
135 WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
136 WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
137 WriteReg_32(DBSC_E3_DBTR5,0x00000027);
138 WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
139 } else { /* 1856Mbps */
140 WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
141 WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
142 WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
143 WriteReg_32(DBSC_E3_DBTR6,0x00000020);
144 } /* ddr_md */
145
146 WriteReg_32(DBSC_E3_DBTR7,0x00060006);
147
148 /* Select setting value in bps */
149 if (ddr_md==0){ /* 1584Mbps */
150 WriteReg_32(DBSC_E3_DBTR8,0x00000020);
151 WriteReg_32(DBSC_E3_DBTR9,0x00000006);
152 WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
153 WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
154 WriteReg_32(DBSC_E3_DBTR12,0x00120012);
155 WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
156 WriteReg_32(DBSC_E3_DBTR14,0x00140005);
157 WriteReg_32(DBSC_E3_DBTR15,0x00050004);
158 WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
159 WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
160 } else { /* 1856Mbps */
161 WriteReg_32(DBSC_E3_DBTR8,0x00000021);
162 WriteReg_32(DBSC_E3_DBTR9,0x00000007);
163 WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
164 WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
165 WriteReg_32(DBSC_E3_DBTR12,0x00140014);
166 WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
167 WriteReg_32(DBSC_E3_DBTR14,0x00170006);
168 WriteReg_32(DBSC_E3_DBTR15,0x00060005);
169 WriteReg_32(DBSC_E3_DBTR16,0x09210507);
170 WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
171 } /* ddr_md */
172
173 WriteReg_32(DBSC_E3_DBTR18,0x00000200);
174
175 /* Select setting value in bps */
176 if (ddr_md==0){ /* 1584Mbps */
177 WriteReg_32(DBSC_E3_DBTR19,0x01000040);
178 WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
179 } else { /* 1856Mbps */
180 WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
181 WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
182 } /* ddr_md */
183
184 WriteReg_32(DBSC_E3_DBTR21,0x00040004);
185 WriteReg_32(DBSC_E3_DBBL,0x00000000);
186 WriteReg_32(DBSC_E3_DBODT0,0x00000001);
187 WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
188 WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
189 WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
190 WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
191 WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
192
193 /* Select setting value in bps */
194 if (ddr_md==0){ /* 1584Mbps */
195 WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
196 WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
197 } else { /* 1856Mbps */
198 WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
199 WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
200 } /* ddr_md */
201
202 /* rev.0.03 add Comment */
203 /****************************************************************************
204 * Initial_Step0( INITBYP )
205 ***************************************************************************/
206 WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
207 WriteReg_32(DBSC_E3_DBCMD,0x01840001);
208 WriteReg_32(DBSC_E3_DBCMD,0x08840000);
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]209 NOTICE("BL2: [COLD_BOOT]\n"); /* rev.0.11 */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]210 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
211 WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
212 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
213 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
214
215 /* rev.0.03 add Comment */
216 /****************************************************************************
217 * Initial_Step1( ZCAL,PLLINIT,DCAL,PHYRST training )
218 ***************************************************************************/
219 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008);
220 WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
221 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
222
223 /* Select setting value in bps */
224 if (ddr_md==0){ /* 1584Mbps */
225 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058904);
226 } else { /* 1856Mbps */
227 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A04);
228 } /* ddr_md */
229
230 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
231 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
232 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
233 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
234 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
235 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
236 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
237
238 /* Select setting value in bps */
239 if (ddr_md==0){ /* 1584Mbps */
240 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
241 } else { /* 1856Mbps */
242 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
243 } /* ddr_md */
244
245 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
246 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
247 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
248 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
249 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
250 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
251
252 /* rev.0.03 add Comment */
253 /****************************************************************************
254 * Initial_Step2( DRAMRST/DRAMINT training )
255 ***************************************************************************/
256 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
257
258 /* Select setting value in bps */
259 if (ddr_md==0){ /* 1584Mbps */
260 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
261 } else { /* 1856Mbps */
262 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
263 } /* ddr_md */
264
265 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090);
266
267 /* Select setting value in bps */
268 if (ddr_md==0){ /* 1584Mbps */
269 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
270 } else { /* 1856Mbps */
271 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
272 } /* ddr_md */
273
274 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
275 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
276
277 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]278 if (byp_ctl == 1) {
279 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
280 } else {
281 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
282 }
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]283 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
284 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
285
286 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
287
288 /* Select setting value in bps */
289 if (ddr_md==0){ /* 1584Mbps */
290 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
291 } else { /* 1856Mbps */
292 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
293 } /* ddr_md */
294
295 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
296 WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
297 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
298
299 /* Select setting value in bps */
300 if (ddr_md==0){ /* 1584Mbps */
301 WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
302 } else { /* 1856Mbps */
303 WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
304 } /* ddr_md */
305
306 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
307
308 /* Select setting value in bps */
309 if (ddr_md==0){ /* 1584Mbps */
310 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
311 } else { /* 1856Mbps */
312 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
313 } /* ddr_md */
314
315 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
316
317 /* Select setting value in bps */
318 if (ddr_md==0){ /* 1584Mbps */
319 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
320 } else { /* 1856Mbps */
321 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
322 } /* ddr_md */
323
324 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
325
326 /* Select setting value in bps */
327 if (ddr_md==0){ /* 1584Mbps */
328 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
329 } else { /* 1856Mbps */
330 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
331 } /* ddr_md */
332
333 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
334
335 /* Select setting value in bps */
336 if (ddr_md==0){ /* 1584Mbps */
337 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
338 } else { /* 1856Mbps */
339 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
340 } /* ddr_md */
341
342 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
343 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
344 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
345
346 /* Select setting value in bps */
347 if (ddr_md==0){ /* 1584Mbps */
348 if (REFRESH_RATE > 3900) {
349 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
350 } else {
351 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
352 }
353 } else { /* 1856Mbps */
354 if (REFRESH_RATE > 3900) {
355 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
356 } else {
357 WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
358 } /* REFRESH_RATE */
359 } /* ddr_md */
360
361 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
362 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
363 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020);
364 WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
365 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A);
366 WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
367 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
368 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
369
370 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
371 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
372 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
373 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
374 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
375 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
376 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
377 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
378 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
379 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
380 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
381 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
382 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
383 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
384 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
385 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
386 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
387 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
388 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
389 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
390 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
391 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
392 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
393 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
394
395 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
396 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010181);
397 WriteReg_32(DBSC_E3_DBCMD,0x08840001);
398 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
399 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
400
401 /* rev.0.03 add Comment */
402 /****************************************************************************
403 * Initial_Step3( WL/QSG training )
404 ***************************************************************************/
405 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
406 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010601);
407 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
408 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
409
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]410 for ( i = 0; i<4; i++){
411 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
412 RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
413 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
414 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
415 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
416 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
417 if ( RegVal_R6 > 0 ){
418 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
419 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
420 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
421 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
422 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
423 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
424 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
425 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
426 } else {
427 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
428 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
429 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
430 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
431 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
432 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
433 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
434 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
435 } /* RegVal_R6 */
436 } /* for i */
437
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]438 /* rev.0.10 move Comment */
439 /****************************************************************************
440 * Initial_Step4( WLADJ training )
441 ***************************************************************************/
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]442 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
443 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
444
445 /* rev.0.08 */
446 if (pdqsr_ctl == 1){}else{
447
448 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
449 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
450 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
451 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
452 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
453 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
454 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
455 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
456
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]457 }
458
459 /* PDR always off */ /* rev.0.10 */
460 if (pdr_ctl == 1) {
461 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
462 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
463 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
464 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
465 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
466 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
467 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
468 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]469 }
470
471 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
472 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
473 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
474 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
475
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]476 /****************************************************************************
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]477 * Initial_Step5(Read Data Bit Deskew)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]478 ***************************************************************************/
479 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
480 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
481
482 /* rev.0.08 */
483 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
484 WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
485 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
486 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
487
488if (pdqsr_ctl == 1){
489 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
490 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
491 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
492 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
493 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
494 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
495 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
496 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
497}
498
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]499 /* PDR dynamic */ /* rev.0.10 */
500 if (pdr_ctl == 1) {
501 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
502 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
503 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
504 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
505 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
506 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
507 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
508 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
509 }
510
511 /****************************************************************************
512 * Initial_Step6(Write Data Bit Deskew)
513 ***************************************************************************/
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]514 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
515 WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
516 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
517 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
518
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]519 /****************************************************************************
520 * Initial_Step7(Read Data Eye Training)
521 ***************************************************************************/
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]522if (pdqsr_ctl == 1){
523 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
524 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
525 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
526 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
527 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
528 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
529 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
530 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
531}
532
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]533 /* PDR always off */ /* rev.0.10 */
534 if (pdr_ctl == 1) {
535 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
536 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
537 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
538 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
539 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
540 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
541 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
542 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
543 }
544
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]545 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
546 WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
547 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
548 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
549
550if (pdqsr_ctl == 1){
551 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
552 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
553 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
554 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
555 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
556 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
557 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
558 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
559}
560
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]561 /* PDR dynamic */ /* rev.0.10 */
562 if (pdr_ctl == 1) {
563 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
564 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
565 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
566 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
567 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
568 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
569 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
570 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
571 }
572
573 /****************************************************************************
574 * Initial_Step8(Write Data Eye Training)
575 ***************************************************************************/
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]576 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
577 WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
578 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
579 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
580
581 /* rev.0.03 add Comment */
582 /****************************************************************************
583 * Initial_Step3_2( DQS Gate Training )
584 ***************************************************************************/
585 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
586 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
587 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
588 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
589 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
590 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
591 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
592 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
593 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
594 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
595 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
596 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
597 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
598 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
599
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]600 for ( i = 0; i < 4; i++){
601 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
602 RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
603 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
604 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
605 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
606 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
607 RegVal_R12 = (RegVal_R5 >> 0x2);
608 if ( RegVal_R12 < RegVal_R6 ){
609 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
610 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
611 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
612 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
613 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
614 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
615 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
616 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
617 } else {
618 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
619 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
620 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
621 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
622 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
623 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
624 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
625 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
626 } /* RegVal_R12 < RegVal_R6 */
627 } /* for i */
628
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]629 /* rev.0.10 move Comment */
630 /****************************************************************************
631 * Initial_Step5-2_7-2( Rd bit Rd eye )
632 ***************************************************************************/
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]633/* rev.0.08 */
634 if (pdqsr_ctl == 1){}else{
635
636 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
637 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
638 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
639 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
640 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
641 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
642 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
643 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
644
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]645 }
646
647 /* PDR always off */ /* rev.0.10 */
648 if (pdr_ctl == 1) {
649 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
650 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
651 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
652 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
653 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
654 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
655 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
656 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]657 }
658
659 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
660 WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
661 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
662 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
663
664
665/* rev.0.08 */
666 if (lcdl_ctl == 1){
667 for (i=0; i< 4; i++) {
668 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
669 dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
670 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
671 bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
672 bdlcount_0c_div2 = (bdlcount_0c >> 1);
673 bdlcount_0c_div4 = (bdlcount_0c >> 2);
674 bdlcount_0c_div8 = (bdlcount_0c >> 3);
675 bdlcount_0c_div16 = (bdlcount_0c >> 4);
676
677 if (ddr_md==0){ /* 1584Mbps */
678 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
679 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
680 } else { /* 1856Mbps */
681 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
682 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
683 } /* ddr_md */
684
685 if (dqsgd_0c > lcdl_judge1) {
686 if (dqsgd_0c <= lcdl_judge2) {
687 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
688 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
689 WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
690 } else {
691 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
692 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
693 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
694 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
695 gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
696 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
697 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
698 WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
699 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
700 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
701 rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
702 rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
703 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
704 WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
705 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
706 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
707 rbd_0c[0] = (RegVal ) & 0x0000001f;
708 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
709 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
710 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
711 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
712 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
713 for (j=0; j< 4; j++) {
714 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
715 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
716 RegVal = RegVal | (rbd_0c[j] <<8*j);
717 }
718 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
719 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
720 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
721 rbd_0c[0] = (RegVal ) & 0x0000001f;
722 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
723 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
724 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
725 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
726 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
727 for (j=0; j< 4; j++) {
728 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
729 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
730 RegVal = RegVal | (rbd_0c[j] <<8*j);
731 }
732 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
733 }
734 }
735 }
736 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
737 WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
738 }
739
740
741 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]742 if (byp_ctl == 1) {
743 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
744 } else {
745 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
746 }
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]747 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
748 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
749
750 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
751 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
752
753 WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
754 WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
755 /* Select setting value in bps */
756 if (ddr_md==0){ /* 1584Mbps */
757 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
758 } else { /* 1856Mbps */
759 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
760 } /* ddr_md */
761
762 WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
763 WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
764 WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
765 WriteReg_32(DBSC_E3_DBACEN,0x00000001);
766
767/* rev.0.08 */
768 if (pdqsr_ctl == 1){
769 WriteReg_32(0xE67F0018,0x00000001);
770 RegVal = ReadReg_32(0x40000000);
771 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
772 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
773 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
774 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
775 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
776 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
777 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
778 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
779 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
780 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
781
782 }
783
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]784 /* PDR dynamic */ /* rev.0.10 */
785 if (pdr_ctl == 1) {
786 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
787 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
788 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
789 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
790 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
791 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
792 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
793 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
794 }
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]795
796 /* rev.0.03 add Comment */
797 /****************************************************************************
798 * Initial_Step9( Initial End )
799 ***************************************************************************/
800 WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
801 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
802
803#ifdef ddr_qos_init_setting /* only for non qos_init */
804 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
805 WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
806 WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
807 WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
808 WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
809 WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
810 WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
811 WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
812 WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
813 WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
814 WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
815 WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
816 WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
817 WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
818 WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
819 WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
820 WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
821 WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
822 WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
823 WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
824 WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
825 WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
826 WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
827 WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
828 WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
829 WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
830 WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
831 WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
832 WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
833 WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
834 WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
835
836/* rev.0.08 */
837 if (pdqsr_ctl == 1){}else{
838 WriteReg_32(0xE67F0018,0x00000001);
839 }
840
841 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
842#endif
843
844 return 1; /* rev.0.04 Restore the return code */
845
846} /* init_ddr */
847
848/* rev.0.04 add function */
849uint32_t recovery_from_backup_mode(void)
850{
851
852 /****************************************************************************
853 * recovery_Step0(DBSC Setting 1) / same "init_ddr"
854 ***************************************************************************/
855 uint32_t RegVal_R2, RegVal_R5, RegVal_R6, RegVal_R7, RegVal_R12, i;
856 uint32_t ddr_md;
857 uint32_t err;
858
859
860/* rev.0.08 */
861 uint32_t RegVal,j;
862 uint32_t dqsgd_0c, bdlcount_0c, bdlcount_0c_div2, bdlcount_0c_div4, bdlcount_0c_div8, bdlcount_0c_div16;
863 uint32_t gatesl_0c, rdqsd_0c, rdqsnd_0c, rbd_0c[4];
864 uint32_t pdqsr_ctl,lcdl_ctl,lcdl_judge1,lcdl_judge2;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]865 /* rev.0.10 */
866 uint32_t pdr_ctl;
867 /* rev.0.11 */
868 uint32_t byp_ctl;
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]869
870/* rev.0.08 */
871 if ((ReadReg_32(0xFFF00044) & 0x000000FF) == 0x00000000) {
872 pdqsr_ctl = 1;
873 lcdl_ctl = 1;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]874 pdr_ctl = 1; /* rev.0.10 */
875 byp_ctl = 1; /* rev.0.11 */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]876 }else {
877 pdqsr_ctl = 0;
878 lcdl_ctl = 0;
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]879 pdr_ctl = 0; /* rev.0.10 */
880 byp_ctl = 0; /* rev.0.11 */
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]881 }
882
883
884 /* Judge the DDR bit rate (ddr_md : 0 = 1584Mbps, 1 = 1856Mbps) */
885 ddr_md = (ReadReg_32(RST_MODEMR)>>19)&BIT0;
886
887 /* 1584Mbps setting */
888 if (ddr_md==0){
889 /* CPG setting ===============================================*/
890 WriteReg_32(CPG_CPGWPR,0x5A5AFFFF);
891 WriteReg_32(CPG_CPGWPCR,0xA5A50000);
892
893 WriteReg_32(CPG_SRCR4,0x20000000);
894
895 WriteReg_32(0xE61500DC,0xe2200000); /* Change to 1584Mbps */
896 while ( (BIT11 & ReadReg_32(CPG_PLLECR)) == 0 );
897
898 WriteReg_32(CPG_SRSTCLR4,0x20000000);
899
900 WriteReg_32(CPG_CPGWPCR,0xA5A50001);
901
902 /* CPG setting ===============================================*/
903 } /* ddr_md */
904
905 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
906 WriteReg_32(DBSC_E3_DBKIND,0x00000007);
907
908#if RCAR_DRAM_DDR3L_MEMCONF == 0
909 WriteReg_32(DBSC_E3_DBMEMCONF00,0x0f030a02);
910#elif RCAR_DRAM_DDR3L_MEMCONF == 1
911 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
912#elif RCAR_DRAM_DDR3L_MEMCONF == 2
913 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030b02);
914#else
915 WriteReg_32(DBSC_E3_DBMEMCONF00,0x10030a02);
916#endif
917
918/* rev.0.08 */
919#if RCAR_DRAM_DDR3L_MEMDUAL == 1
920 RegVal_R2 = (ReadReg_32(0xE6790614));
921 WriteReg_32(0xE6790614,RegVal_R2 | 0x00000003); /* MCS1_N/MODT1 are activated. */
922#endif
923
924 WriteReg_32(DBSC_E3_DBPHYCONF0,0x00000001);
925
926 /* Select setting value in bps */
927 if (ddr_md==0){ /* 1584Mbps */
928 WriteReg_32(DBSC_E3_DBTR0,0x0000000B);
929 WriteReg_32(DBSC_E3_DBTR1,0x00000008);
930 } else { /* 1856Mbps */
931 WriteReg_32(DBSC_E3_DBTR0,0x0000000D);
932 WriteReg_32(DBSC_E3_DBTR1,0x00000009);
933 } /* ddr_md */
934
935 WriteReg_32(DBSC_E3_DBTR2,0x00000000);
936
937 /* Select setting value in bps */
938 if (ddr_md==0){ /* 1584Mbps */
939 WriteReg_32(DBSC_E3_DBTR3,0x0000000B);
940 WriteReg_32(DBSC_E3_DBTR4,0x000B000B);
941 WriteReg_32(DBSC_E3_DBTR5,0x00000027);
942 WriteReg_32(DBSC_E3_DBTR6,0x0000001C);
943 } else { /* 1856Mbps */
944 WriteReg_32(DBSC_E3_DBTR3,0x0000000D);
945 WriteReg_32(DBSC_E3_DBTR4,0x000D000D);
946 WriteReg_32(DBSC_E3_DBTR5,0x0000002D);
947 WriteReg_32(DBSC_E3_DBTR6,0x00000020);
948 } /* ddr_md */
949
950 WriteReg_32(DBSC_E3_DBTR7,0x00060006);
951
952 /* Select setting value in bps */
953 if (ddr_md==0){ /* 1584Mbps */
954 WriteReg_32(DBSC_E3_DBTR8,0x00000020);
955 WriteReg_32(DBSC_E3_DBTR9,0x00000006);
956 WriteReg_32(DBSC_E3_DBTR10,0x0000000C);
957 WriteReg_32(DBSC_E3_DBTR11,0x0000000A);
958 WriteReg_32(DBSC_E3_DBTR12,0x00120012);
959 WriteReg_32(DBSC_E3_DBTR13,0x000000CE);
960 WriteReg_32(DBSC_E3_DBTR14,0x00140005);
961 WriteReg_32(DBSC_E3_DBTR15,0x00050004);
962 WriteReg_32(DBSC_E3_DBTR16,0x071F0305);
963 WriteReg_32(DBSC_E3_DBTR17,0x040C0000);
964 } else { /* 1856Mbps */
965 WriteReg_32(DBSC_E3_DBTR8,0x00000021);
966 WriteReg_32(DBSC_E3_DBTR9,0x00000007);
967 WriteReg_32(DBSC_E3_DBTR10,0x0000000E);
968 WriteReg_32(DBSC_E3_DBTR11,0x0000000C);
969 WriteReg_32(DBSC_E3_DBTR12,0x00140014);
970 WriteReg_32(DBSC_E3_DBTR13,0x000000F2);
971 WriteReg_32(DBSC_E3_DBTR14,0x00170006);
972 WriteReg_32(DBSC_E3_DBTR15,0x00060005);
973 WriteReg_32(DBSC_E3_DBTR16,0x09210507);
974 WriteReg_32(DBSC_E3_DBTR17,0x040E0000);
975 } /* ddr_md */
976
977 WriteReg_32(DBSC_E3_DBTR18,0x00000200);
978
979 /* Select setting value in bps */
980 if (ddr_md==0){ /* 1584Mbps */
981 WriteReg_32(DBSC_E3_DBTR19,0x01000040);
982 WriteReg_32(DBSC_E3_DBTR20,0x020000D6);
983 } else { /* 1856Mbps */
984 WriteReg_32(DBSC_E3_DBTR19,0x0129004B);
985 WriteReg_32(DBSC_E3_DBTR20,0x020000FB);
986 } /* ddr_md */
987
988 WriteReg_32(DBSC_E3_DBTR21,0x00040004);
989 WriteReg_32(DBSC_E3_DBBL,0x00000000);
990 WriteReg_32(DBSC_E3_DBODT0,0x00000001);
991 WriteReg_32(DBSC_E3_DBADJ0,0x00000001);
992 WriteReg_32(DBSC_E3_DBSYSCONF1,0x00000002);
993 WriteReg_32(DBSC_E3_DBDFICNT0,0x00000010);
994 WriteReg_32(DBSC_E3_DBBCAMDIS,0x00000001);
995 WriteReg_32(DBSC_E3_DBSCHRW1,0x00000046);
996
997 /* Select setting value in bps */
998 if (ddr_md==0){ /* 1584Mbps */
999 WriteReg_32(DBSC_E3_SCFCTST0,0x0D050B03);
1000 WriteReg_32(DBSC_E3_SCFCTST1,0x0306030C);
1001 } else { /* 1856Mbps */
1002 WriteReg_32(DBSC_E3_SCFCTST0,0x0C050B03);
1003 WriteReg_32(DBSC_E3_SCFCTST1,0x0305030C);
1004 } /* ddr_md */
1005
1006 /****************************************************************************
1007 * recovery_Step1(PHY setting 1)
1008 ***************************************************************************/
1009 WriteReg_32(DBSC_E3_DBPDLK0,0x0000A55A);
1010 WriteReg_32(DBSC_E3_DBCMD,0x01840001);
1011 WriteReg_32(DBSC_E3_DBCMD,0x0A840000);
1012 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000008); /* DDR_PLLCR */
1013 WriteReg_32(DBSC_E3_DBPDRGD0,0x000B8000);
1014 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003); /* DDR_PGCR1 */
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1015 if (byp_ctl == 1) {
1016 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C720);
1017 } else {
1018 WriteReg_32(DBSC_E3_DBPDRGD0,0x0780C700);
1019 }
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1020 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000020); /* DDR_DXCCR */
1021 WriteReg_32(DBSC_E3_DBPDRGD0,0x00181884);
1022 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000001A); /* DDR_ACIOCR0 */
1023 WriteReg_32(DBSC_E3_DBPDRGD0,0x33C03C10);
1024 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
1025 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1026
1027 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000004);
1028
1029 /* Select setting value in bps */
1030 if (ddr_md==0){ /* 1584Mbps */
1031 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*792/125)-400 + 0x08B00000);
1032 } else { /* 1856Mbps */
1033 WriteReg_32(DBSC_E3_DBPDRGD0,(uint32_t)(REFRESH_RATE*928/125)-400 + 0x0A300000);
1034 } /* ddr_md */
1035
1036 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000022);
1037 WriteReg_32(DBSC_E3_DBPDRGD0,0x1000040B);
1038 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000023);
1039
1040 /* Select setting value in bps */
1041 if (ddr_md==0){ /* 1584Mbps */
1042 WriteReg_32(DBSC_E3_DBPDRGD0,0x2D9C0B66);
1043 } else { /* 1856Mbps */
1044 WriteReg_32(DBSC_E3_DBPDRGD0,0x35A00D77);
1045 } /* ddr_md */
1046
1047 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000024);
1048
1049 /* Select setting value in bps */
1050 if (ddr_md==0){ /* 1584Mbps */
1051 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A88B400);
1052 } else { /* 1856Mbps */
1053 WriteReg_32(DBSC_E3_DBPDRGD0,0x2A8A2C28);
1054 } /* ddr_md */
1055
1056 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000025);
1057
1058 /* Select setting value in bps */
1059 if (ddr_md==0){ /* 1584Mbps */
1060 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005200);
1061 } else { /* 1856Mbps */
1062 WriteReg_32(DBSC_E3_DBPDRGD0,0x30005E00);
1063 } /* ddr_md */
1064
1065 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000026);
1066
1067 /* Select setting value in bps */
1068 if (ddr_md==0){ /* 1584Mbps */
1069 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014A9C9);
1070 } else { /* 1856Mbps */
1071 WriteReg_32(DBSC_E3_DBPDRGD0,0x0014CB49);
1072 } /* ddr_md */
1073
1074 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000027);
1075
1076 /* Select setting value in bps */
1077 if (ddr_md==0){ /* 1584Mbps */
1078 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000D70);
1079 } else { /* 1856Mbps */
1080 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000F14);
1081 } /* ddr_md */
1082
1083 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000028);
1084 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000046);
1085 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000029);
1086
1087 /* Select setting value in bps */
1088 if (ddr_md==0){ /* 1584Mbps */
1089 if (REFRESH_RATE > 3900) {
1090 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000018); /* [7]SRT=0 */
1091 } else {
1092 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000098); /* [7]SRT=1 */
1093 }
1094 } else { /* 1856Mbps */
1095 if (REFRESH_RATE > 3900) {
1096 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000020); /* [7]SRT=0 */
1097 } else {
1098 WriteReg_32(DBSC_E3_DBPDRGD0,0x000000A0); /* [7]SRT=1 */
1099 } /* REFRESH_RATE */
1100 } /* ddr_md */
1101
1102 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
1103 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003047);
1104 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000091);
1105 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
1106 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000095);
1107 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BBAD);
1108 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000099);
1109 WriteReg_32(DBSC_E3_DBPDRGD0,0x0007BB6B);
1110 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021); /* DDR_DSGCR */
1111 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024641E);
1112 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1113 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1114
1115 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1116 WriteReg_32(DBSC_E3_DBPDRGD0,0x40010000);
1117
1118 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1119 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1120
1121 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
1122 WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
1123 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
1124 WriteReg_32(DBSC_E3_DBPDRGD0,0xC4285FBF);
1125 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
1126 WriteReg_32(DBSC_E3_DBPDRGD0,0xC2C59AB5);
1127 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1128
1129 /* Select setting value in bps */
1130 if (ddr_md==0){ /* 1584Mbps */
1131 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
1132 } else { /* 1856Mbps */
1133 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
1134 } /* ddr_md */
1135
1136 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1137
1138 /* Select setting value in bps */
1139 if (ddr_md==0){ /* 1584Mbps */
1140 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
1141 } else { /* 1856Mbps */
1142 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
1143 } /* ddr_md */
1144
1145 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1146 WriteReg_32(DBSC_E3_DBPDRGD0,0x00050001);
1147
1148 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1149 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1150
1151 /* ddr backupmode end */
1152 if(ddrBackup) {
1153 NOTICE("[WARM_BOOT]");
1154 } else {
1155 NOTICE("[COLD_BOOT]");
1156 } /* ddrBackup */
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1157 err=rcar_dram_update_boot_status(ddrBackup);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1158 if(err){
1159 NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
1160 return INITDRAM_ERR_I;
1161 } /* err */
1162
1163 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000092); /* DDR_ZQ0DR */
1164 WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
1165 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000096); /* DDR_ZQ1DR */
1166 WriteReg_32(DBSC_E3_DBPDRGD0,0x04285FBF);
1167 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000009A); /* DDR_ZQ2DR */
1168 WriteReg_32(DBSC_E3_DBPDRGD0,0x02C59AB5);
1169
1170 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1171 WriteReg_32(DBSC_E3_DBPDRGD0,0x08000000);
1172
1173 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1174 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000003);
1175
1176 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1177 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1178
1179 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1180 WriteReg_32(DBSC_E3_DBPDRGD0,0x80010000);
1181
1182 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1183 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1184
1185 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1186 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010073);
1187
1188 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1189 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1190
1191 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1192
1193 /* Select setting value in bps */
1194 if (ddr_md==0){ /* 1584Mbps */
1195 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058900);
1196 } else { /* 1856Mbps */
1197 WriteReg_32(DBSC_E3_DBPDRGD0,0x0C058A00);
1198 } /* ddr_md */
1199
1200 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000090); /* DDR_ZQCR */
1201
1202 /* Select setting value in bps */
1203 if (ddr_md==0){ /* 1584Mbps */
1204 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058900);
1205 } else { /* 1856Mbps */
1206 WriteReg_32(DBSC_E3_DBPDRGD0,0x04058A00);
1207 } /* ddr_md */
1208
1209/* rev0.08 */
1210 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000000C);
1211 WriteReg_32(DBSC_E3_DBPDRGD0,0x18000040);
1212
1213 /****************************************************************************
1214 * recovery_Step2(PHY setting 2)
1215 ***************************************************************************/
1216 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1217 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1218
1219 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A7);
1220 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1221 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A8);
1222 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1223 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A9);
1224 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1225 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C7);
1226 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1227 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C8);
1228 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1229 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C9);
1230 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1231 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E7);
1232 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1233 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E8);
1234 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1235 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E9);
1236 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1237 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000107);
1238 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1239 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000108);
1240 WriteReg_32(DBSC_E3_DBPDRGD0,0x0D0D0D0D);
1241 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000109);
1242 WriteReg_32(DBSC_E3_DBPDRGD0,0x000D0D0D);
1243
1244 WriteReg_32(DBSC_E3_DBCALCNF, (uint32_t)(64000000/REFRESH_RATE) + 0x01000000);
1245 WriteReg_32(DBSC_E3_DBBUS0CNF1,0x00000010);
1246
1247 /* Select setting value in bps */
1248 if (ddr_md==0){ /* 1584Mbps */
1249 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*99/125) + 0x00080000);
1250 } else { /* 1856Mbps */
1251 WriteReg_32(DBSC_E3_DBRFCNF1, (uint32_t)(REFRESH_RATE*116/125) + 0x00080000);
1252 } /* ddr_md */
1253
1254 WriteReg_32(DBSC_E3_DBRFCNF2,0x00010000);
1255 WriteReg_32(DBSC_E3_DBRFEN,0x00000001);
1256 WriteReg_32(DBSC_E3_DBCMD,0x0A840001);
1257 while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
1258
1259 WriteReg_32(DBSC_E3_DBCMD,0x00000000);
1260
1261 WriteReg_32(DBSC_E3_DBCMD,0x04840010);
1262 while ( (BIT0 & ReadReg_32(DBSC_E3_DBWAIT)) != 0 );
1263
1264 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1265 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1266
1267 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001); /* DDR_PIR */
1268 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010701);
1269
1270 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006); /* DDR_PGSR0 */
1271 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1272
1273 for ( i = 0; i<4; i++)
1274 {
1275 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1276 RegVal_R5 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8;
1277 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
1278 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1279 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
1280 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1281
1282 if ( RegVal_R6 > 0 ){
1283 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1284 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1285 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1286 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
1287 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1288 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1289 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1290 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R6);
1291 } else {
1292 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1293 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1294 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1295 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | RegVal_R7);
1296 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1297 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1298 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1299 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + ((RegVal_R5) << 1)) & 0x000000FF));
1300 } /* RegVal_R6 */
1301 } /* for i */
1302
1303 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
1304 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00C0);
1305
1306 /* rev.0.08 */
1307 if (pdqsr_ctl == 1){}else{
1308
1309 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1310 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1311 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1312 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1313 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1314 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1315 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1316 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1317
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1318 }
1319
1320 /* PDR always off */ /* rev.0.10 */
1321 if (pdr_ctl == 1) {
1322 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1323 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1324 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1325 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1326 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1327 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1328 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1329 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1330 }
1331
1332 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1333 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010801);
1334 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1335 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1336
1337 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000005);
1338 WriteReg_32(DBSC_E3_DBPDRGD0,0xC1AA00D8);
1339
1340
1341 /* rev.0.08 */
1342 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1343 WriteReg_32(DBSC_E3_DBPDRGD0,0x00011001);
1344 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1345 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1346
1347if (pdqsr_ctl == 1){
1348 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1349 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1350 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1351 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1352 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1353 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1354 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1355 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1356}
1357
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1358 /* PDR dynamic */ /* rev.0.10 */
1359 if (pdr_ctl==1) {
1360 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1361 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1362 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1363 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1364 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1365 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1366 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1367 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1368 }
1369
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1370 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1371 WriteReg_32(DBSC_E3_DBPDRGD0,0x00012001);
1372 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1373 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1374
1375if (pdqsr_ctl == 1){
1376 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1377 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1378 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1379 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1380 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1381 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1382 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1383 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1384}
1385
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1386 /* PDR always off */ /* rev.0.10 */
1387 if (pdr_ctl == 1) {
1388 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1389 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1390 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1391 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1392 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1393 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1394 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1395 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1396 }
1397
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1398 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1399 WriteReg_32(DBSC_E3_DBPDRGD0,0x00014001);
1400 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1401 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1402
1403if (pdqsr_ctl == 1){
1404 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1405 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1406 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1407 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1408 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1409 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1410 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1411 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1412}
1413
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1414 /* PDR dynamic */ /* rev.0.10 */
1415 if (pdr_ctl == 1) {
1416 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1417 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1418 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1419 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1420 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1421 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1422 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1423 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1424 }
1425
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1426 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1427 WriteReg_32(DBSC_E3_DBPDRGD0,0x00018001);
1428 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1429 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1430
1431 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1432 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1433 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1434 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1435 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1436 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1437 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1438 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C000285);
1439 WriteReg_32(DBSC_E3_DBPDRGA0,0x0000002C);
1440 WriteReg_32(DBSC_E3_DBPDRGD0,0x81003087);
1441 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1442 WriteReg_32(DBSC_E3_DBPDRGD0,0x00010401);
1443 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1444 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1445
1446 for ( i = 0; i < 4; i++){
1447 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1448 RegVal_R5 = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 0x8);
1449 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B4 + i*0x20);
1450 RegVal_R6 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1451 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B3 + i*0x20);
1452 RegVal_R7 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1453 RegVal_R12 = (RegVal_R5 >> 0x2);
1454
1455 if ( RegVal_R12 < RegVal_R6 ){
1456 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1457 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1458 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1459 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R7 + 0x1) & 0x00000007));
1460 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1461 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1462 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1463 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 - (RegVal_R12)) & 0x000000FF));
1464 } else {
1465 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1466 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1467 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B2 + i*0x20);
1468 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | (RegVal_R7 & 0x00000007));
1469 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1470 RegVal_R2 = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1471 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1472 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal_R2 | ((RegVal_R6 + (RegVal_R5) + ((RegVal_R5) >> 1) + (RegVal_R12)) & 0x000000FF));
1473 } /* RegVal_R12 < RegVal_R6 */
1474 } /* for i */
1475
1476/* rev.0.08 */
1477 if (pdqsr_ctl == 1){}else{
1478
1479 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1480 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1481 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1482 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1483 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1484 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1485 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1486 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1487
1488 }
1489
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1490 /* PDR always off */ /* rev.0.10 */
1491 if (pdr_ctl==1) {
1492 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1493 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1494 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1495 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1496 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1497 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1498 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1499 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000008);
1500 }
1501
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1502 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000001);
1503 WriteReg_32(DBSC_E3_DBPDRGD0,0x00015001);
1504 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000006);
1505 while ( (BIT0 & ReadReg_32(DBSC_E3_DBPDRGD0)) == 0 );
1506
1507
1508/* rev.0.08 */
1509 if (lcdl_ctl == 1){
1510 for (i=0; i< 4; i++) {
1511 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B0 + i*0x20);
1512 dqsgd_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x000000FF);
1513 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000B1 + i*0x20);
1514 bdlcount_0c = ((ReadReg_32(DBSC_E3_DBPDRGD0) & 0x0000FF00) >> 8);
1515 bdlcount_0c_div2 = (bdlcount_0c >> 1);
1516 bdlcount_0c_div4 = (bdlcount_0c >> 2);
1517 bdlcount_0c_div8 = (bdlcount_0c >> 3);
1518 bdlcount_0c_div16 = (bdlcount_0c >> 4);
1519
1520 if (ddr_md==0){ /* 1584Mbps */
1521 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 + bdlcount_0c_div8 ;
1522 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 + bdlcount_0c_div16 ;
1523 } else { /* 1856Mbps */
1524 lcdl_judge1 = bdlcount_0c_div2 + bdlcount_0c_div4 ;
1525 lcdl_judge2 = bdlcount_0c + bdlcount_0c_div4 ;
1526 } /* ddr_md */
1527
1528 if (dqsgd_0c > lcdl_judge1) {
1529 if (dqsgd_0c <= lcdl_judge2) {
1530 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
1531 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1532 WriteReg_32(DBSC_E3_DBPDRGD0,((dqsgd_0c - bdlcount_0c_div8) | RegVal));
1533 } else {
1534 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B0 + i * 0x20);
1535 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFF00);
1536 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1537 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
1538 gatesl_0c = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0x00000007);
1539 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000B2 + i * 0x20);
1540 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xFFFFFFF8);
1541 WriteReg_32(DBSC_E3_DBPDRGD0, (RegVal|(gatesl_0c + 1)));
1542 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
1543 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1544 rdqsd_0c = (RegVal & 0x0000FF00) >> 8;
1545 rdqsnd_0c = (RegVal & 0x00FF0000) >> 16;
1546 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AF + i * 0x20);
1547 WriteReg_32(DBSC_E3_DBPDRGD0, ((RegVal & 0xFF0000FF)|((rdqsd_0c + bdlcount_0c_div4) << 8)|((rdqsnd_0c + bdlcount_0c_div4) << 16)));
1548 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
1549 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1550 rbd_0c[0] = (RegVal ) & 0x0000001f;
1551 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
1552 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
1553 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
1554 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AA + i * 0x20);
1555 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
1556 for (j=0; j< 4; j++) {
1557 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
1558 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
1559 RegVal = RegVal | (rbd_0c[j] <<8*j);
1560 }
1561 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1562 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
1563 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0));
1564 rbd_0c[0] = (RegVal ) & 0x0000001f;
1565 rbd_0c[1] = (RegVal >> 8) & 0x0000001f;
1566 rbd_0c[2] = (RegVal >> 16) & 0x0000001f;
1567 rbd_0c[3] = (RegVal >> 24) & 0x0000001f;
1568 WriteReg_32(DBSC_E3_DBPDRGA0, 0x000000AB + i * 0x20);
1569 RegVal = (ReadReg_32(DBSC_E3_DBPDRGD0) & 0xE0E0E0E0);
1570 for (j=0; j< 4; j++) {
1571 rbd_0c[j] = (rbd_0c[j] + bdlcount_0c_div4);
1572 if (rbd_0c[j] > 0x1F) rbd_0c[j] = 0x1F;
1573 RegVal = RegVal | (rbd_0c[j] <<8*j);
1574 }
1575 WriteReg_32(DBSC_E3_DBPDRGD0, RegVal);
1576 }
1577 }
1578 }
1579 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000002);
1580 WriteReg_32(DBSC_E3_DBPDRGD0,0x07D81E37);
1581 }
1582
1583
1584
1585 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000003);
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1586 if (byp_ctl==1) {
1587 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C720);
1588 } else {
1589 WriteReg_32(DBSC_E3_DBPDRGD0,0x0380C700);
1590 }
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1591 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000007);
1592 while ( (BIT30 & ReadReg_32(DBSC_E3_DBPDRGD0)) != 0 );
1593 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000021);
1594 WriteReg_32(DBSC_E3_DBPDRGD0,0x0024643E);
1595
1596 /****************************************************************************
1597 * recovery_Step3(DBSC Setting 2)
1598 ***************************************************************************/
1599 WriteReg_32(DBSC_E3_DBDFICUPDCNF,0x40100001);
1600 WriteReg_32(DBSC_E3_DBACEN,0x00000001);
1601
1602/* rev.0.08 */
1603 if (pdqsr_ctl == 1){
1604 WriteReg_32(0xE67F0018,0x00000001);
1605 RegVal = ReadReg_32(0x40000000);
1606 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000000);
1607 WriteReg_32(DBSC_E3_DBPDRGD0,RegVal);
1608 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A0);
1609 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1610 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C0);
1611 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1612 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E0);
1613 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1614 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000100);
1615 WriteReg_32(DBSC_E3_DBPDRGD0,0x7C0002C5);
1616
Marek Vasut432d7672018-12-12 18:06:39 +0100[diff] [blame^]1617 }
1618
1619 /* PDR dynamic */ /* rev.0.10 */
1620 if (pdr_ctl == 1) {
1621 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000A3);
1622 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1623 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000C3);
1624 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1625 WriteReg_32(DBSC_E3_DBPDRGA0,0x000000E3);
1626 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
1627 WriteReg_32(DBSC_E3_DBPDRGA0,0x00000103);
1628 WriteReg_32(DBSC_E3_DBPDRGD0,0x00000000);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1629 }
1630
1631
1632 WriteReg_32(DBSC_E3_DBPDLK0,0x00000000);
1633 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
1634
1635#ifdef ddr_qos_init_setting /* only for non qos_init */
1636 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00001234);
1637 WriteReg_32(DBSC_E3_DBCAM0CNF1,0x00043218);
1638 WriteReg_32(DBSC_E3_DBCAM0CNF2,0x000000F4);
1639 WriteReg_32(DBSC_E3_DBSCHCNT0,0x000f0037);
1640 WriteReg_32(DBSC_E3_DBSCHSZ0,0x00000001);
1641 WriteReg_32(DBSC_E3_DBSCHRW0,0x22421111);
1642 WriteReg_32(DBSC_E3_SCFCTST2,0x012F1123);
1643 WriteReg_32(DBSC_E3_DBSCHQOS00,0x00000F00);
1644 WriteReg_32(DBSC_E3_DBSCHQOS01,0x00000B00);
1645 WriteReg_32(DBSC_E3_DBSCHQOS02,0x00000000);
1646 WriteReg_32(DBSC_E3_DBSCHQOS03,0x00000000);
1647 WriteReg_32(DBSC_E3_DBSCHQOS40,0x00000300);
1648 WriteReg_32(DBSC_E3_DBSCHQOS41,0x000002F0);
1649 WriteReg_32(DBSC_E3_DBSCHQOS42,0x00000200);
1650 WriteReg_32(DBSC_E3_DBSCHQOS43,0x00000100);
1651 WriteReg_32(DBSC_E3_DBSCHQOS90,0x00000100);
1652 WriteReg_32(DBSC_E3_DBSCHQOS91,0x000000F0);
1653 WriteReg_32(DBSC_E3_DBSCHQOS92,0x000000A0);
1654 WriteReg_32(DBSC_E3_DBSCHQOS93,0x00000040);
1655 WriteReg_32(DBSC_E3_DBSCHQOS130,0x00000100);
1656 WriteReg_32(DBSC_E3_DBSCHQOS131,0x000000F0);
1657 WriteReg_32(DBSC_E3_DBSCHQOS132,0x000000A0);
1658 WriteReg_32(DBSC_E3_DBSCHQOS133,0x00000040);
1659 WriteReg_32(DBSC_E3_DBSCHQOS140,0x000000C0);
1660 WriteReg_32(DBSC_E3_DBSCHQOS141,0x000000B0);
1661 WriteReg_32(DBSC_E3_DBSCHQOS142,0x00000080);
1662 WriteReg_32(DBSC_E3_DBSCHQOS143,0x00000040);
1663 WriteReg_32(DBSC_E3_DBSCHQOS150,0x00000040);
1664 WriteReg_32(DBSC_E3_DBSCHQOS151,0x00000030);
1665 WriteReg_32(DBSC_E3_DBSCHQOS152,0x00000020);
1666 WriteReg_32(DBSC_E3_DBSCHQOS153,0x00000010);
1667
1668/* rev.0.08 */
1669 if (pdqsr_ctl == 1){}else{
1670 WriteReg_32(0xE67F0018,0x00000001);
1671 }
1672
1673 WriteReg_32(DBSC_E3_DBSYSCNT0,0x00000000);
1674#endif
1675
1676 return 1;
1677
1678} /* recovery_from_backup_mode */
1679
1680/*******************************************************************************
1681 * init_ddr : MD19=0,DDR3L,1584Mbps / MD19=1,DDR3L,1856Mbps
1682 ******************************************************************************/
1683
1684/*******************************************************************************
1685 * DDR Initialize entry for IPL
1686 ******************************************************************************/
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1687int32_t rcar_dram_init(void)
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1688{
1689 uint32_t dataL;
1690 uint32_t failcount;
1691 uint32_t md=0;
1692 uint32_t ddr=0;
1693
1694 md = *((volatile uint32_t*)RST_MODEMR);
1695 ddr = (md & 0x00080000) >> 19;
1696 if(ddr == 0x0){
1697 NOTICE("BL2: DDR1584(%s)", RCAR_E3_DDR_VERSION);
1698 }
1699 else if(ddr == 0x1){
1700 NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
1701 } /* ddr */
1702
ldts0a596b42018-11-06 10:17:12 +0100[diff] [blame]1703 rcar_dram_get_boot_status(&ddrBackup);
Jorge Ramirez-Ortiz47503d22018-09-23 09:36:52 +0200[diff] [blame]1704
1705 if(ddrBackup==DRAM_BOOT_STATUS_WARM){
1706 dataL=recovery_from_backup_mode(); /* WARM boot */
1707 } else {
1708 dataL=init_ddr(); /* COLD boot */
1709 } /* ddrBackup */
1710
1711 if(dataL==1){
1712 failcount =0;
1713 } else {
1714 failcount =1;
1715 } /* dataL */
1716
1717 NOTICE("..%d\n",failcount); /* rev.0.05 */
1718
1719 if(failcount==0){
1720 return INITDRAM_OK;
1721 } else {
1722 return INITDRAM_NG;
1723 } /* failcount */
1724} /* InitDram */
1725
1726/*******************************************************************************
1727 * END
1728 ******************************************************************************/