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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Madhukar Pappireddy7a539802020-01-16 22:21:33 -06002 * Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta4f6ad662013-10-25 09:08:21 +01005 */
6
Dan Handleyed6ff952014-05-14 17:44:19 +01007#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
9#include <lib/xlat_tables/xlat_tables_defs.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010010
11OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT)
12OUTPUT_ARCH(PLATFORM_LINKER_ARCH)
Jeenu Viswambharan2a30a752014-03-11 11:06:45 +000013ENTRY(bl31_entrypoint)
Achin Gupta4f6ad662013-10-25 09:08:21 +010014
15
16MEMORY {
Juan Castillofd8c0772014-09-16 10:40:35 +010017 RAM (rwx): ORIGIN = BL31_BASE, LENGTH = BL31_LIMIT - BL31_BASE
Samuel Holland31a14e12018-10-17 21:40:18 -050018#if SEPARATE_NOBITS_REGION
19 NOBITS (rw!a): ORIGIN = BL31_NOBITS_BASE, LENGTH = BL31_NOBITS_LIMIT - BL31_NOBITS_BASE
20#else
21#define NOBITS RAM
22#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010023}
24
Caesar Wangd90f43e2016-10-11 09:36:00 +080025#ifdef PLAT_EXTRA_LD_SCRIPT
26#include <plat.ld.S>
27#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +010028
29SECTIONS
30{
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000031 . = BL31_BASE;
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +000032 ASSERT(. == ALIGN(PAGE_SIZE),
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000033 "BL31_BASE address is not aligned on a page boundary.")
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
Soby Mathew4e28c202018-10-14 08:09:22 +010035 __BL31_START__ = .;
36
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010037#if SEPARATE_CODE_AND_RODATA
38 .text . : {
39 __TEXT_START__ = .;
40 *bl31_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050041 *(SORT_BY_ALIGNMENT(.text*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010042 *(.vectors)
Roberto Vargasd93fde32018-04-11 11:53:31 +010043 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010044 __TEXT_END__ = .;
45 } >RAM
46
47 .rodata . : {
48 __RODATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -050049 *(SORT_BY_ALIGNMENT(.rodata*))
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010050
51 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
52 . = ALIGN(8);
53 __RT_SVC_DESCS_START__ = .;
54 KEEP(*(rt_svc_descs))
55 __RT_SVC_DESCS_END__ = .;
56
57#if ENABLE_PMF
58 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
59 . = ALIGN(8);
60 __PMF_SVC_DESCS_START__ = .;
61 KEEP(*(pmf_svc_descs))
62 __PMF_SVC_DESCS_END__ = .;
63#endif /* ENABLE_PMF */
64
65 /*
66 * Ensure 8-byte alignment for cpu_ops so that its fields are also
67 * aligned. Also ensure cpu_ops inclusion.
68 */
69 . = ALIGN(8);
70 __CPU_OPS_START__ = .;
71 KEEP(*(cpu_ops))
72 __CPU_OPS_END__ = .;
73
Soby Mathew4e28c202018-10-14 08:09:22 +010074 /*
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000075 * Keep the .got section in the RO section as it is patched
Soby Mathew4e28c202018-10-14 08:09:22 +010076 * prior to enabling the MMU and having the .got in RO is better for
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000077 * security. GOT is a table of addresses so ensure 8-byte alignment.
Soby Mathew4e28c202018-10-14 08:09:22 +010078 */
Soby Mathew2b3fc1d2018-12-12 14:33:11 +000079 . = ALIGN(8);
Soby Mathew4e28c202018-10-14 08:09:22 +010080 __GOT_START__ = .;
81 *(.got)
82 __GOT_END__ = .;
83
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010084 /* Place pubsub sections for events */
85 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000086#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +010087
Roberto Vargasd93fde32018-04-11 11:53:31 +010088 . = ALIGN(PAGE_SIZE);
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +010089 __RODATA_END__ = .;
90 } >RAM
91#else
Sandrine Bailleux8d69a032013-11-27 09:38:52 +000092 ro . : {
93 __RO_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +000094 *bl31_entrypoint.o(.text*)
Samuel Holland23f5e542019-10-20 16:11:25 -050095 *(SORT_BY_ALIGNMENT(.text*))
96 *(SORT_BY_ALIGNMENT(.rodata*))
Achin Gupta7421b462014-02-01 18:53:26 +000097
Andrew Thoelkee01ea342014-03-18 07:13:52 +000098 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
Achin Gupta7421b462014-02-01 18:53:26 +000099 . = ALIGN(8);
100 __RT_SVC_DESCS_START__ = .;
Andrew Thoelkee01ea342014-03-18 07:13:52 +0000101 KEEP(*(rt_svc_descs))
Achin Gupta7421b462014-02-01 18:53:26 +0000102 __RT_SVC_DESCS_END__ = .;
103
Yatharth Kochar9518d022016-03-11 14:20:19 +0000104#if ENABLE_PMF
105 /* Ensure 8-byte alignment for descriptors and ensure inclusion */
106 . = ALIGN(8);
107 __PMF_SVC_DESCS_START__ = .;
108 KEEP(*(pmf_svc_descs))
109 __PMF_SVC_DESCS_END__ = .;
110#endif /* ENABLE_PMF */
111
Soby Mathewc704cbc2014-08-14 11:33:56 +0100112 /*
113 * Ensure 8-byte alignment for cpu_ops so that its fields are also
114 * aligned. Also ensure cpu_ops inclusion.
115 */
116 . = ALIGN(8);
117 __CPU_OPS_START__ = .;
118 KEEP(*(cpu_ops))
119 __CPU_OPS_END__ = .;
120
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000121 /*
122 * Keep the .got section in the RO section as it is patched
123 * prior to enabling the MMU and having the .got in RO is better for
124 * security. GOT is a table of addresses so ensure 8-byte alignment.
125 */
126 . = ALIGN(8);
127 __GOT_START__ = .;
128 *(.got)
129 __GOT_END__ = .;
130
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100131 /* Place pubsub sections for events */
132 . = ALIGN(8);
Antonio Nino Diaze0f90632018-12-14 00:18:21 +0000133#include <lib/el3_runtime/pubsub_events.h>
Jeenu Viswambharane3f22002017-09-22 08:32:10 +0100134
Achin Guptab739f222014-01-18 16:50:09 +0000135 *(.vectors)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000136 __RO_END_UNALIGNED__ = .;
137 /*
138 * Memory page(s) mapped to this section will be marked as read-only,
139 * executable. No RW data from the next section must creep in.
140 * Ensure the rest of the current memory page is unused.
141 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100142 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000143 __RO_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144 } >RAM
Sandrine Bailleuxf91f1442016-07-08 14:37:40 +0100145#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100146
Soby Mathewc704cbc2014-08-14 11:33:56 +0100147 ASSERT(__CPU_OPS_END__ > __CPU_OPS_START__,
148 "cpu_ops not defined for this platform.")
149
Paul Beesleydb4e25a2019-10-14 15:27:12 +0000150#if SPM_MM
Ard Biesheuvel447d56f2019-01-06 10:07:24 +0100151#ifndef SPM_SHIM_EXCEPTIONS_VMA
152#define SPM_SHIM_EXCEPTIONS_VMA RAM
153#endif
154
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100155 /*
156 * Exception vectors of the SPM shim layer. They must be aligned to a 2K
157 * address, but we need to place them in a separate page so that we can set
158 * individual permissions to them, so the actual alignment needed is 4K.
159 *
160 * There's no need to include this into the RO section of BL31 because it
161 * doesn't need to be accessed by BL31.
162 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000163 spm_shim_exceptions : ALIGN(PAGE_SIZE) {
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100164 __SPM_SHIM_EXCEPTIONS_START__ = .;
165 *(.spm_shim_exceptions)
Roberto Vargasd93fde32018-04-11 11:53:31 +0100166 . = ALIGN(PAGE_SIZE);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100167 __SPM_SHIM_EXCEPTIONS_END__ = .;
Ard Biesheuvel447d56f2019-01-06 10:07:24 +0100168 } >SPM_SHIM_EXCEPTIONS_VMA AT>RAM
169
170 PROVIDE(__SPM_SHIM_EXCEPTIONS_LMA__ = LOADADDR(spm_shim_exceptions));
171 . = LOADADDR(spm_shim_exceptions) + SIZEOF(spm_shim_exceptions);
Antonio Nino Diazc41f2062017-10-24 10:07:35 +0100172#endif
173
Achin Guptae9c4a642015-09-11 16:03:13 +0100174 /*
175 * Define a linker symbol to mark start of the RW memory area for this
176 * image.
177 */
178 __RW_START__ = . ;
179
Douglas Raillard306593d2017-02-24 18:14:15 +0000180 /*
181 * .data must be placed at a lower address than the stacks if the stack
182 * protector is enabled. Alternatively, the .data.stack_protector_canary
183 * section can be placed independently of the main .data section.
184 */
185 .data . : {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000186 __DATA_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -0500187 *(SORT_BY_ALIGNMENT(.data*))
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000188 __DATA_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100189 } >RAM
190
Soby Mathew4e28c202018-10-14 08:09:22 +0100191 /*
192 * .rela.dyn needs to come after .data for the read-elf utility to parse
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000193 * this section correctly. Ensure 8-byte alignment so that the fields of
194 * RELA data structure are aligned.
Soby Mathew4e28c202018-10-14 08:09:22 +0100195 */
Soby Mathew2b3fc1d2018-12-12 14:33:11 +0000196 . = ALIGN(8);
Soby Mathew4e28c202018-10-14 08:09:22 +0100197 __RELA_START__ = .;
198 .rela.dyn . : {
199 } >RAM
200 __RELA_END__ = .;
201
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100202#ifdef BL31_PROGBITS_LIMIT
Juan Castillo7d199412015-12-14 09:35:25 +0000203 ASSERT(. <= BL31_PROGBITS_LIMIT, "BL31 progbits has exceeded its limit.")
Sandrine Bailleuxe2e0c652014-06-16 16:12:27 +0100204#endif
205
Samuel Holland31a14e12018-10-17 21:40:18 -0500206#if SEPARATE_NOBITS_REGION
207 /*
208 * Define a linker symbol to mark end of the RW memory area for this
209 * image.
210 */
Madhukar Pappireddy7a539802020-01-16 22:21:33 -0600211 . = ALIGN(PAGE_SIZE);
Samuel Holland31a14e12018-10-17 21:40:18 -0500212 __RW_END__ = .;
213 __BL31_END__ = .;
214
215 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
216
217 . = BL31_NOBITS_BASE;
218 ASSERT(. == ALIGN(PAGE_SIZE),
219 "BL31 NOBITS base address is not aligned on a page boundary.")
220
221 __NOBITS_START__ = .;
222#endif
223
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000224 stacks (NOLOAD) : {
225 __STACKS_START__ = .;
226 *(tzfw_normal_stacks)
227 __STACKS_END__ = .;
Samuel Holland31a14e12018-10-17 21:40:18 -0500228 } >NOBITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100229
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000230 /*
231 * The .bss section gets initialised to 0 at runtime.
Douglas Raillard21362a92016-12-02 13:51:54 +0000232 * Its base address should be 16-byte aligned for better performance of the
233 * zero-initialization code.
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000234 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100235 .bss (NOLOAD) : ALIGN(16) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000236 __BSS_START__ = .;
Samuel Holland23f5e542019-10-20 16:11:25 -0500237 *(SORT_BY_ALIGNMENT(.bss*))
Achin Gupta4f6ad662013-10-25 09:08:21 +0100238 *(COMMON)
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100239#if !USE_COHERENT_MEM
240 /*
241 * Bakery locks are stored in normal .bss memory
242 *
243 * Each lock's data is spread across multiple cache lines, one per CPU,
244 * but multiple locks can share the same cache line.
245 * The compiler will allocate enough memory for one CPU's bakery locks,
246 * the remaining cache lines are allocated by the linker script
247 */
248 . = ALIGN(CACHE_WRITEBACK_GRANULE);
249 __BAKERY_LOCK_START__ = .;
Varun Wadekar77c382c2019-01-30 08:26:20 -0800250 __PERCPU_BAKERY_LOCK_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100251 *(bakery_lock)
252 . = ALIGN(CACHE_WRITEBACK_GRANULE);
Varun Wadekar77c382c2019-01-30 08:26:20 -0800253 __PERCPU_BAKERY_LOCK_END__ = .;
254 __PERCPU_BAKERY_LOCK_SIZE__ = ABSOLUTE(__PERCPU_BAKERY_LOCK_END__ - __PERCPU_BAKERY_LOCK_START__);
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100255 . = . + (__PERCPU_BAKERY_LOCK_SIZE__ * (PLATFORM_CORE_COUNT - 1));
256 __BAKERY_LOCK_END__ = .;
Roberto Vargas00996942017-11-13 13:41:58 +0000257
258 /*
259 * If BL31 doesn't use any bakery lock then __PERCPU_BAKERY_LOCK_SIZE__
260 * will be zero. For this reason, the only two valid values for
261 * __PERCPU_BAKERY_LOCK_SIZE__ are 0 or the platform defined value
262 * PLAT_PERCPU_BAKERY_LOCK_SIZE.
263 */
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100264#ifdef PLAT_PERCPU_BAKERY_LOCK_SIZE
Roberto Vargas00996942017-11-13 13:41:58 +0000265 ASSERT((__PERCPU_BAKERY_LOCK_SIZE__ == 0) || (__PERCPU_BAKERY_LOCK_SIZE__ == PLAT_PERCPU_BAKERY_LOCK_SIZE),
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100266 "PLAT_PERCPU_BAKERY_LOCK_SIZE does not match bakery lock requirements");
267#endif
268#endif
Yatharth Kochar9518d022016-03-11 14:20:19 +0000269
270#if ENABLE_PMF
271 /*
272 * Time-stamps are stored in normal .bss memory
273 *
274 * The compiler will allocate enough memory for one CPU's time-stamps,
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000275 * the remaining memory for other CPUs is allocated by the
Yatharth Kochar9518d022016-03-11 14:20:19 +0000276 * linker script
277 */
278 . = ALIGN(CACHE_WRITEBACK_GRANULE);
279 __PMF_TIMESTAMP_START__ = .;
280 KEEP(*(pmf_timestamp_array))
281 . = ALIGN(CACHE_WRITEBACK_GRANULE);
282 __PMF_PERCPU_TIMESTAMP_END__ = .;
283 __PERCPU_TIMESTAMP_SIZE__ = ABSOLUTE(. - __PMF_TIMESTAMP_START__);
284 . = . + (__PERCPU_TIMESTAMP_SIZE__ * (PLATFORM_CORE_COUNT - 1));
285 __PMF_TIMESTAMP_END__ = .;
286#endif /* ENABLE_PMF */
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000287 __BSS_END__ = .;
Samuel Holland31a14e12018-10-17 21:40:18 -0500288 } >NOBITS
Achin Gupta4f6ad662013-10-25 09:08:21 +0100289
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000290 /*
Jeenu Viswambharan97cc9ee2014-02-24 15:20:28 +0000291 * The xlat_table section is for full, aligned page tables (4K).
Achin Guptaa0cd9892014-02-09 13:30:38 +0000292 * Removing them from .bss avoids forcing 4K alignment on
Antonio Nino Diaz7c2a3ca2018-02-23 15:07:54 +0000293 * the .bss section. The tables are initialized to zero by the translation
294 * tables library.
Achin Guptaa0cd9892014-02-09 13:30:38 +0000295 */
296 xlat_table (NOLOAD) : {
297 *(xlat_table)
Samuel Holland31a14e12018-10-17 21:40:18 -0500298 } >NOBITS
Achin Guptaa0cd9892014-02-09 13:30:38 +0000299
Soby Mathew2ae20432015-01-08 18:02:44 +0000300#if USE_COHERENT_MEM
Achin Guptaa0cd9892014-02-09 13:30:38 +0000301 /*
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000302 * The base address of the coherent memory section must be page-aligned (4K)
303 * to guarantee that the coherent data are stored on their own pages and
304 * are not mixed with normal data. This is required to set up the correct
305 * memory attributes for the coherent data page tables.
306 */
Antonio Nino Diaz2ce2b092017-11-15 11:45:35 +0000307 coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) {
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000308 __COHERENT_RAM_START__ = .;
Andrew Thoelkee466c9f2015-09-10 11:39:36 +0100309 /*
310 * Bakery locks are stored in coherent memory
311 *
312 * Each lock's data is contiguous and fully allocated by the compiler
313 */
314 *(bakery_lock)
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000315 *(tzfw_coherent_mem)
316 __COHERENT_RAM_END_UNALIGNED__ = .;
317 /*
318 * Memory page(s) mapped to this section will be marked
319 * as device memory. No other unexpected data must creep in.
320 * Ensure the rest of the current memory page is unused.
321 */
Roberto Vargasd93fde32018-04-11 11:53:31 +0100322 . = ALIGN(PAGE_SIZE);
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000323 __COHERENT_RAM_END__ = .;
Samuel Holland31a14e12018-10-17 21:40:18 -0500324 } >NOBITS
Soby Mathew2ae20432015-01-08 18:02:44 +0000325#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100326
Samuel Holland31a14e12018-10-17 21:40:18 -0500327#if SEPARATE_NOBITS_REGION
328 /*
329 * Define a linker symbol to mark end of the NOBITS memory area for this
330 * image.
331 */
332 __NOBITS_END__ = .;
333
334 ASSERT(. <= BL31_NOBITS_LIMIT, "BL31 NOBITS region has exceeded its limit.")
335#else
Achin Guptae9c4a642015-09-11 16:03:13 +0100336 /*
337 * Define a linker symbol to mark end of the RW memory area for this
338 * image.
339 */
340 __RW_END__ = .;
Sandrine Bailleux8d69a032013-11-27 09:38:52 +0000341 __BL31_END__ = .;
Achin Gupta4f6ad662013-10-25 09:08:21 +0100342
Juan Castillo7d199412015-12-14 09:35:25 +0000343 ASSERT(. <= BL31_LIMIT, "BL31 image has exceeded its limit.")
Samuel Holland31a14e12018-10-17 21:40:18 -0500344#endif
Achin Gupta4f6ad662013-10-25 09:08:21 +0100345}