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Sandrine Bailleux798140d2014-07-17 16:06:39 +01001#
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +00002# Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Sandrine Bailleux798140d2014-07-17 16:06:39 +01003#
dp-armfa3cf0b2017-05-03 09:38:09 +01004# SPDX-License-Identifier: BSD-3-Clause
Sandrine Bailleux798140d2014-07-17 16:06:39 +01005#
6
Achin Gupta1fa7eb62015-11-03 14:18:34 +00007JUNO_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
8 drivers/arm/gic/v2/gicv2_main.c \
9 drivers/arm/gic/v2/gicv2_helpers.c \
10 plat/common/plat_gicv2.c \
11 plat/arm/common/arm_gicv2.c
12
Vikram Kanigirifbb13012016-02-15 11:54:14 +000013JUNO_INTERCONNECT_SOURCES := drivers/arm/cci/cci.c \
14 plat/arm/common/arm_cci.c
15
Soby Mathew9c708b52016-02-26 14:23:19 +000016JUNO_SECURITY_SOURCES := drivers/arm/tzc/tzc400.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000017 plat/arm/board/juno/juno_security.c \
dp-arm8f59e152017-02-27 12:21:43 +000018 plat/arm/board/juno/juno_trng.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000019 plat/arm/common/arm_tzc400.c
20
dp-armb3263b32017-02-28 14:43:15 +000021ifneq (${ENABLE_STACK_PROTECTOR}, 0)
22JUNO_SECURITY_SOURCES += plat/arm/board/juno/juno_stack_protector.c
23endif
Vikram Kanigirifbb13012016-02-15 11:54:14 +000024
Sathees Balya22576072018-09-03 17:41:13 +010025# Select SCMI/SDS drivers instead of SCPI/BOM driver for communicating with the
26# SCP during power management operations and for SCP RAM Firmware transfer.
27CSS_USE_SCMI_SDS_DRIVER := 1
28
Antonio Nino Diaz09d58762019-01-23 19:06:55 +000029PLAT_INCLUDES := -Iplat/arm/board/juno/include
Juan Castillo921b8772014-09-05 17:29:38 +010030
Antonio Nino Diazcbc68262018-10-10 11:02:34 +010031PLAT_BL_COMMON_SOURCES := plat/arm/board/juno/${ARCH}/juno_helpers.S \
32 plat/arm/board/juno/juno_common.c
Juan Castillo921b8772014-09-05 17:29:38 +010033
Yatharth Kocharede39cb2016-11-14 12:01:04 +000034# Flag to enable support for AArch32 state on JUNO
35JUNO_AARCH32_EL3_RUNTIME := 0
36$(eval $(call assert_boolean,JUNO_AARCH32_EL3_RUNTIME))
37$(eval $(call add_define,JUNO_AARCH32_EL3_RUNTIME))
38
Summer Qin13b95c22018-03-02 15:51:14 +080039# Flag to enable support for TZMP1 on JUNO
40JUNO_TZMP1 := 0
41$(eval $(call assert_boolean,JUNO_TZMP1))
42ifeq (${JUNO_TZMP1}, 1)
43$(eval $(call add_define,JUNO_TZMP1))
44endif
45
Soby Mathewbf169232017-11-14 14:10:10 +000046ifeq (${JUNO_AARCH32_EL3_RUNTIME}, 1)
47# Include BL32 in FIP
48NEED_BL32 := yes
49# BL31 is not required
50override BL31_SOURCES =
51
52# The BL32 needs to be built separately invoking the AARCH32 compiler and
53# be specifed via `BL32` build option.
54 ifneq (${ARCH}, aarch32)
55 override BL32_SOURCES =
56 endif
57endif
58
Yatharth Kocharede39cb2016-11-14 12:01:04 +000059ifeq (${ARCH},aarch64)
Dan Handley7bef8002015-03-19 19:22:44 +000060BL1_SOURCES += lib/cpus/aarch64/cortex_a53.S \
Brendan Jackmana443d222015-10-30 16:25:12 +000061 lib/cpus/aarch64/cortex_a57.S \
Juan Castillob6132f12015-10-06 14:01:35 +010062 lib/cpus/aarch64/cortex_a72.S \
Sathees Balya22576072018-09-03 17:41:13 +010063 plat/arm/board/juno/juno_err.c \
Yatharth Kochar736a3bf2015-10-11 14:14:55 +010064 plat/arm/board/juno/juno_bl1_setup.c \
Aditya Angadi20b48412019-04-16 11:29:14 +053065 drivers/arm/sp805/sp805.c \
dp-armb3263b32017-02-28 14:43:15 +000066 ${JUNO_INTERCONNECT_SOURCES} \
67 ${JUNO_SECURITY_SOURCES}
Juan Castillo921b8772014-09-05 17:29:38 +010068
Ambroise Vincentfa42c9e2019-07-04 14:58:45 +010069BL2_SOURCES += drivers/arm/sp805/sp805.c \
70 lib/utils/mem_region.c \
Sathees Balya22576072018-09-03 17:41:13 +010071 plat/arm/board/juno/juno_err.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010072 plat/arm/board/juno/juno_bl2_setup.c \
73 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000074 ${JUNO_SECURITY_SOURCES}
Juan Castillo921b8772014-09-05 17:29:38 +010075
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000076BL2U_SOURCES += ${JUNO_SECURITY_SOURCES}
Yatharth Kochar3a11eda2015-10-14 15:28:11 +010077
Antonio Nino Diazd7da2f82018-10-10 11:14:44 +010078BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
79 lib/cpus/aarch64/cortex_a53.S \
Soby Mathew61e8d0b2015-10-12 17:32:29 +010080 lib/cpus/aarch64/cortex_a57.S \
Brendan Jackmana443d222015-10-30 16:25:12 +000081 lib/cpus/aarch64/cortex_a72.S \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010082 lib/utils/mem_region.c \
Chandni Cherukurie4bf6a02018-11-14 13:43:59 +053083 plat/arm/board/juno/juno_pm.c \
Soby Mathew47e43f22016-02-01 14:04:34 +000084 plat/arm/board/juno/juno_topology.c \
Roberto Vargasb96ee4b2018-08-06 13:35:31 +010085 plat/arm/common/arm_nor_psci_mem_protect.c \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000086 ${JUNO_GIC_SOURCES} \
Vikram Kanigirifbb13012016-02-15 11:54:14 +000087 ${JUNO_INTERCONNECT_SOURCES} \
Vikram Kanigiri70752bb2016-02-10 14:50:53 +000088 ${JUNO_SECURITY_SOURCES}
Sathees Balya22576072018-09-03 17:41:13 +010089
90ifeq (${CSS_USE_SCMI_SDS_DRIVER},1)
Antonio Nino Diaz09d58762019-01-23 19:06:55 +000091BL1_SOURCES += drivers/arm/css/sds/sds.c
Yatharth Kocharede39cb2016-11-14 12:01:04 +000092endif
Juan Castillo921b8772014-09-05 17:29:38 +010093
Sathees Balya22576072018-09-03 17:41:13 +010094endif
95
Deepak Pandeyb0971f92018-05-25 12:43:30 +053096ifneq (${RESET_TO_BL31},0)
Sandrine Bailleux1e32d322019-01-07 15:35:37 +010097 $(error "Using BL31 as the reset vector is not supported on ${PLAT} platform. \
Deepak Pandeyb0971f92018-05-25 12:43:30 +053098 Please set RESET_TO_BL31 to 0.")
99endif
100
Sathees Balya6f07a602018-11-02 14:56:06 +0000101ifeq ($(USE_ROMLIB),1)
102all : bl1_romlib.bin
103endif
104
105bl1_romlib.bin : $(BUILD_PLAT)/bl1.bin $(BUILD_PLAT)/romlib/romlib.bin
106 @echo "Building combined BL1 and ROMLIB binary for Juno $@"
107 ./lib/romlib/gen_combined_bl1_romlib.sh -o bl1_romlib.bin $(BUILD_PLAT)
108
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100109# Errata workarounds for Cortex-A53:
Ambroise Vincentbde42462019-02-22 14:19:16 +0000110ERRATA_A53_819472 := 1
111ERRATA_A53_824069 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100112ERRATA_A53_826319 := 1
Ambroise Vincentbde42462019-02-22 14:19:16 +0000113ERRATA_A53_827319 := 1
Douglas Raillardd56fb042017-06-19 15:38:02 +0100114ERRATA_A53_835769 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100115ERRATA_A53_836870 := 1
Douglas Raillardd56fb042017-06-19 15:38:02 +0100116ERRATA_A53_843419 := 1
Andre Przywara00eefd92016-10-06 16:54:53 +0100117ERRATA_A53_855873 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100118
119# Errata workarounds for Cortex-A57:
Vikram Kanigirieade34c2016-01-20 15:57:35 +0000120ERRATA_A57_806969 := 0
Antonio Nino Diaz3f13c352017-02-24 11:39:22 +0000121ERRATA_A57_813419 := 1
Vikram Kanigirieade34c2016-01-20 15:57:35 +0000122ERRATA_A57_813420 := 1
Ambroise Vincentbde42462019-02-22 14:19:16 +0000123ERRATA_A57_814670 := 1
124ERRATA_A57_817169 := 1
Douglas Raillard71d4fe22017-02-28 17:56:15 +0000125ERRATA_A57_826974 := 1
126ERRATA_A57_826977 := 1
127ERRATA_A57_828024 := 1
128ERRATA_A57_829520 := 1
129ERRATA_A57_833471 := 1
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100130ERRATA_A57_859972 := 0
Douglas Raillard71d4fe22017-02-28 17:56:15 +0000131
Eleanor Bonnici8392aab2017-08-04 15:03:51 +0100132# Errata workarounds for Cortex-A72:
133ERRATA_A72_859971 := 0
Soby Mathew937488b2014-09-22 14:13:34 +0100134
135# Enable option to skip L1 data cache flush during the Cortex-A57 cluster
136# power down sequence
137SKIP_A57_L1_FLUSH_PWR_DWN := 1
Dan Handley7bef8002015-03-19 19:22:44 +0000138
David Cunadoc5b0c0f2017-10-31 23:19:21 +0000139# Do not enable SVE
140ENABLE_SVE_FOR_NS := 0
141
Antonio Nino Diaz4e6408c2019-01-23 16:23:07 +0000142# Enable the dynamic translation tables library.
143ifeq (${ARCH},aarch32)
144 ifeq (${RESET_TO_SP_MIN},1)
145 BL32_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
146 endif
147else
148 ifeq (${RESET_TO_BL31},1)
149 BL31_CFLAGS += -DPLAT_XLAT_TABLES_DYNAMIC=1
150 endif
151endif
152
Louis Mayencourt65cac462019-07-29 10:40:17 +0100153# Add the FDT_SOURCES and options for Dynamic Config
154FDT_SOURCES += plat/arm/board/juno/fdts/${PLAT}_tb_fw_config.dts
155TB_FW_CONFIG := ${BUILD_PLAT}/fdts/${PLAT}_tb_fw_config.dtb
156
157# Add the TB_FW_CONFIG to FIP and specify the same to certtool
158$(eval $(call TOOL_ADD_PAYLOAD,${TB_FW_CONFIG},--tb-fw-config))
159
Antonio Nino Diazcbc68262018-10-10 11:02:34 +0100160include plat/arm/board/common/board_common.mk
Dan Handley7bef8002015-03-19 19:22:44 +0000161include plat/arm/common/arm_common.mk
162include plat/arm/soc/common/soc_css.mk
163include plat/arm/css/common/css_common.mk