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Achin Gupta4f6ad662013-10-25 09:08:21 +01001/*
Dan Handleye83b0ca2014-01-14 18:17:09 +00002 * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
Achin Gupta4f6ad662013-10-25 09:08:21 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010032#include <asm_macros.S>
Dan Handley2bd4ef22014-04-09 13:14:54 +010033#include <psci.h>
Achin Gupta4f6ad662013-10-25 09:08:21 +010034
35 .globl psci_aff_on_finish_entry
36 .globl psci_aff_suspend_finish_entry
37 .globl __psci_cpu_off
38 .globl __psci_cpu_suspend
Achin Gupta42c52802014-05-09 19:32:25 +010039 .globl psci_power_down_wfi
Achin Gupta4f6ad662013-10-25 09:08:21 +010040
Achin Gupta4f6ad662013-10-25 09:08:21 +010041 /* -----------------------------------------------------
42 * This cpu has been physically powered up. Depending
43 * upon whether it was resumed from suspend or simply
44 * turned on, call the common power on finisher with
45 * the handlers (chosen depending upon original state).
46 * For ease, the finisher is called with coherent
47 * stacks. This allows the cluster/cpu finishers to
48 * enter coherency and enable the mmu without running
49 * into issues. We switch back to normal stacks once
50 * all this is done.
51 * -----------------------------------------------------
52 */
Andrew Thoelke38bde412014-03-18 13:46:55 +000053func psci_aff_on_finish_entry
Achin Gupta4f6ad662013-10-25 09:08:21 +010054 adr x23, psci_afflvl_on_finishers
55 b psci_aff_common_finish_entry
56
57psci_aff_suspend_finish_entry:
58 adr x23, psci_afflvl_suspend_finishers
59
60psci_aff_common_finish_entry:
61 adr x22, psci_afflvl_power_on_finish
Achin Guptab739f222014-01-18 16:50:09 +000062
63 /* ---------------------------------------------
64 * Exceptions should not occur at this point.
65 * Set VBAR in order to handle and report any
66 * that do occur
67 * ---------------------------------------------
68 */
69 adr x0, early_exceptions
70 msr vbar_el3, x0
71 isb
72
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000073 /* ---------------------------------------------
74 * Use SP_EL0 for the C runtime stack.
75 * ---------------------------------------------
76 */
77 msr spsel, #0
Jeenu Viswambharancaa84932014-02-06 10:36:15 +000078
Andrew Thoelkef977ed82014-04-28 12:32:02 +010079 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +010080 bl platform_set_coherent_stack
81
82 /* ---------------------------------------------
83 * Call the finishers starting from affinity
84 * level 0.
85 * ---------------------------------------------
86 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +010087 mrs x0, mpidr_el1
Achin Guptaa45e3972013-12-05 15:10:48 +000088 bl get_power_on_target_afflvl
89 cmp x0, xzr
90 b.lt _panic
Achin Gupta4f6ad662013-10-25 09:08:21 +010091 mov x3, x23
92 mov x2, x0
Achin Gupta4f6ad662013-10-25 09:08:21 +010093 mov x1, #MPIDR_AFFLVL0
Andrew Thoelkef977ed82014-04-28 12:32:02 +010094 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +010095 blr x22
Achin Gupta4f6ad662013-10-25 09:08:21 +010096
97 /* --------------------------------------------
98 * Give ourselves a stack allocated in Normal
99 * -IS-WBWA memory
100 * --------------------------------------------
101 */
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100102 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100103 bl platform_set_stack
104
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000105 b el3_exit
Achin Gupta4f6ad662013-10-25 09:08:21 +0100106_panic:
107 b _panic
108
109 /* -----------------------------------------------------
110 * The following two stubs give the calling cpu a
111 * coherent stack to allow flushing of caches without
112 * suffering from stack coherency issues
113 * -----------------------------------------------------
114 */
Andrew Thoelke38bde412014-03-18 13:46:55 +0000115func __psci_cpu_off
Achin Gupta4f6ad662013-10-25 09:08:21 +0100116 func_prologue
117 sub sp, sp, #0x10
118 stp x19, x20, [sp, #0]
119 mov x19, sp
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100120 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100121 bl platform_set_coherent_stack
122 bl psci_cpu_off
Achin Gupta4f6ad662013-10-25 09:08:21 +0100123 mov sp, x19
124 ldp x19, x20, [sp,#0]
125 add sp, sp, #0x10
126 func_epilogue
127 ret
128
Andrew Thoelke38bde412014-03-18 13:46:55 +0000129func __psci_cpu_suspend
Achin Gupta4f6ad662013-10-25 09:08:21 +0100130 func_prologue
131 sub sp, sp, #0x20
132 stp x19, x20, [sp, #0]
133 stp x21, x22, [sp, #0x10]
134 mov x19, sp
135 mov x20, x0
136 mov x21, x1
137 mov x22, x2
Andrew Thoelkef977ed82014-04-28 12:32:02 +0100138 mrs x0, mpidr_el1
Achin Gupta4f6ad662013-10-25 09:08:21 +0100139 bl platform_set_coherent_stack
140 mov x0, x20
141 mov x1, x21
142 mov x2, x22
143 bl psci_cpu_suspend
Achin Gupta4f6ad662013-10-25 09:08:21 +0100144 mov sp, x19
145 ldp x21, x22, [sp,#0x10]
146 ldp x19, x20, [sp,#0]
147 add sp, sp, #0x20
148 func_epilogue
149 ret
150
Achin Gupta42c52802014-05-09 19:32:25 +0100151 /* --------------------------------------------
152 * This function is called to indicate to the
153 * power controller that it is safe to power
154 * down this cpu. It should not exit the wfi
155 * and will be released from reset upon power
156 * up. 'wfi_spill' is used to catch erroneous
157 * exits from wfi.
158 * --------------------------------------------
159 */
160func psci_power_down_wfi
Andrew Thoelke42e75a72014-04-28 12:28:39 +0100161 dsb sy // ensure write buffer empty
Achin Gupta4f6ad662013-10-25 09:08:21 +0100162 wfi
163wfi_spill:
164 b wfi_spill
165