| Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame^] | 1 | /* |
| 2 | * Copyright (c) 2013, ARM Limited. All rights reserved. |
| 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
| 31 | #include <arch.h> |
| 32 | #include <platform.h> |
| 33 | #include <psci.h> |
| 34 | #include <psci_private.h> |
| 35 | #include <asm_macros.S> |
| 36 | |
| 37 | .globl psci_aff_on_finish_entry |
| 38 | .globl psci_aff_suspend_finish_entry |
| 39 | .globl __psci_cpu_off |
| 40 | .globl __psci_cpu_suspend |
| 41 | |
| 42 | .section platform_code, "ax"; .align 3 |
| 43 | |
| 44 | /* ----------------------------------------------------- |
| 45 | * This cpu has been physically powered up. Depending |
| 46 | * upon whether it was resumed from suspend or simply |
| 47 | * turned on, call the common power on finisher with |
| 48 | * the handlers (chosen depending upon original state). |
| 49 | * For ease, the finisher is called with coherent |
| 50 | * stacks. This allows the cluster/cpu finishers to |
| 51 | * enter coherency and enable the mmu without running |
| 52 | * into issues. We switch back to normal stacks once |
| 53 | * all this is done. |
| 54 | * ----------------------------------------------------- |
| 55 | */ |
| 56 | psci_aff_on_finish_entry: |
| 57 | adr x23, psci_afflvl_on_finishers |
| 58 | b psci_aff_common_finish_entry |
| 59 | |
| 60 | psci_aff_suspend_finish_entry: |
| 61 | adr x23, psci_afflvl_suspend_finishers |
| 62 | |
| 63 | psci_aff_common_finish_entry: |
| 64 | adr x22, psci_afflvl_power_on_finish |
| 65 | bl read_mpidr |
| 66 | mov x19, x0 |
| 67 | bl platform_set_coherent_stack |
| 68 | |
| 69 | /* --------------------------------------------- |
| 70 | * Call the finishers starting from affinity |
| 71 | * level 0. |
| 72 | * --------------------------------------------- |
| 73 | */ |
| 74 | bl get_max_afflvl |
| 75 | mov x3, x23 |
| 76 | mov x2, x0 |
| 77 | mov x0, x19 |
| 78 | mov x1, #MPIDR_AFFLVL0 |
| 79 | blr x22 |
| 80 | mov x21, x0 |
| 81 | |
| 82 | /* -------------------------------------------- |
| 83 | * Give ourselves a stack allocated in Normal |
| 84 | * -IS-WBWA memory |
| 85 | * -------------------------------------------- |
| 86 | */ |
| 87 | mov x0, x19 |
| 88 | bl platform_set_stack |
| 89 | |
| 90 | /* -------------------------------------------- |
| 91 | * Restore the context id. value |
| 92 | * -------------------------------------------- |
| 93 | */ |
| 94 | mov x0, x21 |
| 95 | |
| 96 | /* -------------------------------------------- |
| 97 | * Jump back to the non-secure world assuming |
| 98 | * that the elr and spsr setup has been done |
| 99 | * by the finishers |
| 100 | * -------------------------------------------- |
| 101 | */ |
| 102 | eret |
| 103 | _panic: |
| 104 | b _panic |
| 105 | |
| 106 | /* ----------------------------------------------------- |
| 107 | * The following two stubs give the calling cpu a |
| 108 | * coherent stack to allow flushing of caches without |
| 109 | * suffering from stack coherency issues |
| 110 | * ----------------------------------------------------- |
| 111 | */ |
| 112 | __psci_cpu_off: |
| 113 | func_prologue |
| 114 | sub sp, sp, #0x10 |
| 115 | stp x19, x20, [sp, #0] |
| 116 | mov x19, sp |
| 117 | bl read_mpidr |
| 118 | bl platform_set_coherent_stack |
| 119 | bl psci_cpu_off |
| 120 | mov x1, #PSCI_E_SUCCESS |
| 121 | cmp x0, x1 |
| 122 | b.eq final_wfi |
| 123 | mov sp, x19 |
| 124 | ldp x19, x20, [sp,#0] |
| 125 | add sp, sp, #0x10 |
| 126 | func_epilogue |
| 127 | ret |
| 128 | |
| 129 | __psci_cpu_suspend: |
| 130 | func_prologue |
| 131 | sub sp, sp, #0x20 |
| 132 | stp x19, x20, [sp, #0] |
| 133 | stp x21, x22, [sp, #0x10] |
| 134 | mov x19, sp |
| 135 | mov x20, x0 |
| 136 | mov x21, x1 |
| 137 | mov x22, x2 |
| 138 | bl read_mpidr |
| 139 | bl platform_set_coherent_stack |
| 140 | mov x0, x20 |
| 141 | mov x1, x21 |
| 142 | mov x2, x22 |
| 143 | bl psci_cpu_suspend |
| 144 | mov x1, #PSCI_E_SUCCESS |
| 145 | cmp x0, x1 |
| 146 | b.eq final_wfi |
| 147 | mov sp, x19 |
| 148 | ldp x21, x22, [sp,#0x10] |
| 149 | ldp x19, x20, [sp,#0] |
| 150 | add sp, sp, #0x20 |
| 151 | func_epilogue |
| 152 | ret |
| 153 | |
| 154 | final_wfi: |
| 155 | dsb sy |
| 156 | wfi |
| 157 | wfi_spill: |
| 158 | b wfi_spill |
| 159 | |