blob: 696a5774e0478dc82473e4e23f14b7ab1eb81e27 [file] [log] [blame]
Varun Wadekarecd6a5a2018-04-09 17:48:58 -07001/*
2 * Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <arch.h>
8#include <asm_macros.S>
9#include <plat/common/common_def.h>
10#include <memctrl_v2.h>
11#include <tegra_def.h>
12
Varun Wadekarda865de2017-11-10 13:27:29 -080013#define TEGRA194_STATE_SYSTEM_SUSPEND 0x5C7
14#define TEGRA194_STATE_SYSTEM_RESUME 0x600D
Pritesh Raithathafc8f2c52017-10-26 17:06:02 +053015#define TEGRA194_SMMU_CTX_SIZE 0x80B
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070016
17 .align 4
Varun Wadekar362a6b22017-11-10 11:04:42 -080018 .globl tegra194_cpu_reset_handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070019
20/* CPU reset handler routine */
Varun Wadekar362a6b22017-11-10 11:04:42 -080021func tegra194_cpu_reset_handler
Varun Wadekarda865de2017-11-10 13:27:29 -080022 /* check if we are exiting system suspend state */
23 adr x0, __tegra194_system_suspend_state
24 ldr x1, [x0]
25 mov x2, #TEGRA194_STATE_SYSTEM_SUSPEND
26 lsl x2, x2, #16
27 add x2, x2, #TEGRA194_STATE_SYSTEM_SUSPEND
28 cmp x1, x2
29 bne boot_cpu
30
31 /* set system resume state */
32 mov x1, #TEGRA194_STATE_SYSTEM_RESUME
33 lsl x1, x1, #16
34 mov x2, #TEGRA194_STATE_SYSTEM_RESUME
35 add x1, x1, x2
36 str x1, [x0]
37 dsb sy
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070038
Varun Wadekarda865de2017-11-10 13:27:29 -080039 /* prepare to relocate to TZSRAM */
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070040 mov x0, #BL31_BASE
Varun Wadekar362a6b22017-11-10 11:04:42 -080041 adr x1, __tegra194_cpu_reset_handler_end
42 adr x2, __tegra194_cpu_reset_handler_data
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070043 ldr x2, [x2, #8]
44
45 /* memcpy16 */
46m_loop16:
47 cmp x2, #16
48 b.lt m_loop1
49 ldp x3, x4, [x1], #16
50 stp x3, x4, [x0], #16
51 sub x2, x2, #16
52 b m_loop16
53 /* copy byte per byte */
54m_loop1:
55 cbz x2, boot_cpu
56 ldrb w3, [x1], #1
57 strb w3, [x0], #1
58 subs x2, x2, #1
59 b.ne m_loop1
60
61boot_cpu:
Varun Wadekar362a6b22017-11-10 11:04:42 -080062 adr x0, __tegra194_cpu_reset_handler_data
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070063 ldr x0, [x0]
64 br x0
Varun Wadekar362a6b22017-11-10 11:04:42 -080065endfunc tegra194_cpu_reset_handler
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070066
67 /*
Varun Wadekar362a6b22017-11-10 11:04:42 -080068 * Tegra194 reset data (offset 0x0 - 0x2490)
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070069 *
Stefan Kristianssonfa871a62017-03-20 14:19:46 +020070 * 0x0000: secure world's entrypoint
71 * 0x0008: BL31 size (RO + RW)
72 * 0x0010: SMMU context start
73 * 0x2490: SMMU context end
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070074 */
75
76 .align 4
Varun Wadekar362a6b22017-11-10 11:04:42 -080077 .type __tegra194_cpu_reset_handler_data, %object
78 .globl __tegra194_cpu_reset_handler_data
79__tegra194_cpu_reset_handler_data:
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070080 .quad tegra_secure_entrypoint
81 .quad __BL31_END__ - BL31_BASE
Varun Wadekare0c222f2017-11-10 13:23:34 -080082
Varun Wadekarda865de2017-11-10 13:27:29 -080083 .globl __tegra194_system_suspend_state
84__tegra194_system_suspend_state:
85 .quad 0
86
Varun Wadekare0c222f2017-11-10 13:23:34 -080087 .align 4
88__tegra194_smmu_context:
Varun Wadekar362a6b22017-11-10 11:04:42 -080089 .rept TEGRA194_SMMU_CTX_SIZE
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070090 .quad 0
91 .endr
Varun Wadekar362a6b22017-11-10 11:04:42 -080092 .size __tegra194_cpu_reset_handler_data, \
93 . - __tegra194_cpu_reset_handler_data
Varun Wadekarecd6a5a2018-04-09 17:48:58 -070094
95 .align 4
Varun Wadekar362a6b22017-11-10 11:04:42 -080096 .globl __tegra194_cpu_reset_handler_end
97__tegra194_cpu_reset_handler_end:
Varun Wadekare0c222f2017-11-10 13:23:34 -080098
99 .globl tegra194_get_cpu_reset_handler_size
100 .globl tegra194_get_cpu_reset_handler_base
101 .globl tegra194_get_smmu_ctx_offset
Varun Wadekarda865de2017-11-10 13:27:29 -0800102 .globl tegra194_set_system_suspend_entry
Varun Wadekare0c222f2017-11-10 13:23:34 -0800103
104/* return size of the CPU reset handler */
105func tegra194_get_cpu_reset_handler_size
106 adr x0, __tegra194_cpu_reset_handler_end
107 adr x1, tegra194_cpu_reset_handler
108 sub x0, x0, x1
109 ret
110endfunc tegra194_get_cpu_reset_handler_size
111
112/* return the start address of the CPU reset handler */
113func tegra194_get_cpu_reset_handler_base
114 adr x0, tegra194_cpu_reset_handler
115 ret
116endfunc tegra194_get_cpu_reset_handler_base
117
118/* return the size of the SMMU context */
119func tegra194_get_smmu_ctx_offset
120 adr x0, __tegra194_smmu_context
121 adr x1, tegra194_cpu_reset_handler
122 sub x0, x0, x1
123 ret
124endfunc tegra194_get_smmu_ctx_offset
Varun Wadekarda865de2017-11-10 13:27:29 -0800125
126/* set system suspend state before SC7 entry */
127func tegra194_set_system_suspend_entry
128 mov x0, #TEGRA_MC_BASE
129 mov x3, #MC_SECURITY_CFG3_0
130 ldr w1, [x0, x3]
131 lsl x1, x1, #32
132 mov x3, #MC_SECURITY_CFG0_0
133 ldr w2, [x0, x3]
134 orr x3, x1, x2 /* TZDRAM base */
135 adr x0, __tegra194_system_suspend_state
136 adr x1, tegra194_cpu_reset_handler
137 sub x2, x0, x1 /* offset in TZDRAM */
138 mov x0, #TEGRA194_STATE_SYSTEM_SUSPEND
139 lsl x0, x0, #16
140 add x0, x0, #TEGRA194_STATE_SYSTEM_SUSPEND
141 str x0, [x3, x2] /* set value in TZDRAM */
142 dsb sy
143 ret
144endfunc tegra194_set_system_suspend_entry