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git01.mediatek.com / filogic / atf / 5f8e1a0ca34571cdc1af0ea29210bf278d79e49b / . / include / lib / cpus / aarch64 / cortex_a77.h
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Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]1/*
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +0000[diff] [blame]2 * Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Balint Dobszaycc942642019-07-03 13:02:56 +0200[diff] [blame]7#ifndef CORTEX_A77_H
8#define CORTEX_A77_H
Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]9
Antonio Nino Diaz5e79cfe2019-02-11 13:34:15 +0000[diff] [blame]10#include <lib/utils_def.h>
11
Balint Dobszaycc942642019-07-03 13:02:56 +0200[diff] [blame]12/* Cortex-A77 MIDR */
13#define CORTEX_A77_MIDR U(0x410FD0D0)
Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]14
15/*******************************************************************************
16 * CPU Extended Control register specific definitions.
17 ******************************************************************************/
Balint Dobszaycc942642019-07-03 13:02:56 +0200[diff] [blame]18#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]19
20/*******************************************************************************
21 * CPU Power Control register specific definitions.
22 ******************************************************************************/
Balint Dobszaycc942642019-07-03 13:02:56 +0200[diff] [blame]23#define CORTEX_A77_CPUPWRCTLR_EL1 S3_0_C15_C2_7
24#define CORTEX_A77_CPUPWRCTLR_EL1_CORE_PWRDN_BIT (U(1) << 0)
Joel Hutton9463cae2018-05-04 15:09:47 +0100[diff] [blame]25
Balint Dobszaycc942642019-07-03 13:02:56 +0200[diff] [blame]26#endif /* CORTEX_A77_H */