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git01.mediatek.com / filogic / atf / 5f2b012194f44f29d44efdf77ba38075c34d4e52 / . / plat / nvidia / tegra / include / t132 / tegra_def.h
blob: 065989d327576c497fa891b381f20bd3497bf3bb [file] [log] [blame]
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]1/*
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]2 * Copyright (c) 2015-2017, ARM Limited and Contributors. All rights reserved.
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]3 *
dp-armfa3cf0b2017-05-03 09:38:09 +0100[diff] [blame]4 * SPDX-License-Identifier: BSD-3-Clause
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]5 */
6
7#ifndef __TEGRA_DEF_H__
8#define __TEGRA_DEF_H__
9
10#include <platform_def.h>
11
12/*******************************************************************************
13 * This value is used by the PSCI implementation during the `SYSTEM_SUSPEND`
14 * call as the `state-id` field in the 'power state' parameter.
15 ******************************************************************************/
Varun Wadekara78bb1b2015-08-07 10:03:00 +0530[diff] [blame]16#define PSTATE_ID_SOC_POWERDN 0xD
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]17
18/*******************************************************************************
Varun Wadekar3ce54992016-01-19 13:55:19 -0800[diff] [blame]19 * Platform power states (used by PSCI framework)
20 *
21 * - PLAT_MAX_RET_STATE should be less than lowest PSTATE_ID
22 * - PLAT_MAX_OFF_STATE should be greater than the highest PSTATE_ID
23 ******************************************************************************/
24#define PLAT_MAX_RET_STATE 1
25#define PLAT_MAX_OFF_STATE (PSTATE_ID_SOC_POWERDN + 1)
26
27/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]28 * GIC memory map
29 ******************************************************************************/
30#define TEGRA_GICD_BASE 0x50041000
31#define TEGRA_GICC_BASE 0x50042000
32
33/*******************************************************************************
34 * Tegra micro-seconds timer constants
35 ******************************************************************************/
36#define TEGRA_TMRUS_BASE 0x60005010
Steven Kao4d160ac2016-12-23 16:05:13 +0800[diff] [blame]37#define TEGRA_TMRUS_SIZE 0x1000
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]38
39/*******************************************************************************
40 * Tegra Clock and Reset Controller constants
41 ******************************************************************************/
42#define TEGRA_CAR_RESET_BASE 0x60006000
43
44/*******************************************************************************
45 * Tegra Flow Controller constants
46 ******************************************************************************/
47#define TEGRA_FLOWCTRL_BASE 0x60007000
48
49/*******************************************************************************
50 * Tegra Secure Boot Controller constants
51 ******************************************************************************/
52#define TEGRA_SB_BASE 0x6000C200
53
54/*******************************************************************************
55 * Tegra Exception Vectors constants
56 ******************************************************************************/
57#define TEGRA_EVP_BASE 0x6000F000
58
59/*******************************************************************************
Varun Wadekar28dcc212016-07-20 10:28:51 -0700[diff] [blame]60 * Tegra Miscellaneous register constants
61 ******************************************************************************/
62#define TEGRA_MISC_BASE 0x70000000
63#define HARDWARE_REVISION_OFFSET 0x804
64
65/*******************************************************************************
Varun Wadekard2014c62015-10-29 10:37:28 +0530[diff] [blame]66 * Tegra UART controller base addresses
67 ******************************************************************************/
68#define TEGRA_UARTA_BASE 0x70006000
69#define TEGRA_UARTB_BASE 0x70006040
70#define TEGRA_UARTC_BASE 0x70006200
71#define TEGRA_UARTD_BASE 0x70006300
72#define TEGRA_UARTE_BASE 0x70006400
73
74/*******************************************************************************
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]75 * Tegra Power Mgmt Controller constants
76 ******************************************************************************/
77#define TEGRA_PMC_BASE 0x7000E400
78
79/*******************************************************************************
80 * Tegra Memory Controller constants
81 ******************************************************************************/
82#define TEGRA_MC_BASE 0x70019000
83
Varun Wadekar64443ca2016-12-12 16:14:57 -0800[diff] [blame]84/* TZDRAM carveout configuration registers */
85#define MC_SECURITY_CFG0_0 0x70
86#define MC_SECURITY_CFG1_0 0x74
87#define MC_SECURITY_CFG3_0 0x9BC
88
89/* Video Memory carveout configuration registers */
90#define MC_VIDEO_PROTECT_BASE_HI 0x978
91#define MC_VIDEO_PROTECT_BASE_LO 0x648
92#define MC_VIDEO_PROTECT_SIZE_MB 0x64c
93
Varun Wadekar0dc91812015-12-30 15:06:41 -0800[diff] [blame]94/*******************************************************************************
95 * Tegra TZRAM constants
96 ******************************************************************************/
97#define TEGRA_TZRAM_BASE 0x7C010000
98#define TEGRA_TZRAM_SIZE 0x10000
99
Varun Wadekar0f3baa02015-07-16 11:36:33 +0530[diff] [blame]100#endif /* __TEGRA_DEF_H__ */