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Hadi Asyrafi616da772019-06-27 11:34:03 +08001/*
BenjaminLimJLa4a43272022-04-06 10:19:16 +08002 * Copyright (c) 2019-2022, Intel Corporation. All rights reserved.
Hadi Asyrafi616da772019-06-27 11:34:03 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Hadi Asyrafif0fa8072019-10-23 17:02:55 +08007#ifndef SOCFPGA_PRIVATE_H
8#define SOCFPGA_PRIVATE_H
9
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080010
11#define EMMC_DESC_SIZE (1<<20)
12
13#define EMMC_INIT_PARAMS(base, clk) \
14 { .bus_width = MMC_BUS_WIDTH_4, \
15 .clk_rate = (clk), \
16 .desc_base = (base), \
17 .desc_size = EMMC_DESC_SIZE, \
18 .flags = 0, \
19 .reg_base = SOCFPGA_MMC_REG_BASE \
20 }
21
22typedef enum {
23 BOOT_SOURCE_FPGA = 0,
24 BOOT_SOURCE_SDMMC,
25 BOOT_SOURCE_NAND,
26 BOOT_SOURCE_RSVD,
27 BOOT_SOURCE_QSPI
28} boot_source_type;
Hadi Asyrafi616da772019-06-27 11:34:03 +080029
30/*******************************************************************************
31 * Function and variable prototypes
32 ******************************************************************************/
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080033
34void enable_nonsecure_access(void);
35
36void socfpga_io_setup(int boot_source);
37
Hadi Asyrafi616da772019-06-27 11:34:03 +080038void socfgpa_configure_mmu_el3(unsigned long total_base,
39 unsigned long total_size,
40 unsigned long ro_start,
41 unsigned long ro_limit,
42 unsigned long coh_start,
43 unsigned long coh_limit);
44
45
46void socfpga_configure_mmu_el1(unsigned long total_base,
47 unsigned long total_size,
48 unsigned long ro_start,
49 unsigned long ro_limit,
50 unsigned long coh_start,
51 unsigned long coh_limit);
52
53void socfpga_delay_timer_init(void);
54
55void socfpga_gic_driver_init(void);
56
BenjaminLimJLa4a43272022-04-06 10:19:16 +080057void socfpga_delay_timer_init_args(void);
58
Hadi Asyrafi616da772019-06-27 11:34:03 +080059uint32_t socfpga_get_spsr_for_bl32_entry(void);
60
61uint32_t socfpga_get_spsr_for_bl33_entry(void);
62
63unsigned long socfpga_get_ns_image_entrypoint(void);
64
Hadi Asyrafi0563a852019-10-22 12:59:32 +080065void plat_secondary_cpus_bl31_entry(void);
Hadi Asyrafi616da772019-06-27 11:34:03 +080066
Hadi Asyrafif0fa8072019-10-23 17:02:55 +080067#endif /* SOCFPGA_PRIVATE_H */