David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 1 | /* |
Govindraj Raja | eee28e7 | 2023-08-01 15:52:40 -0500 | [diff] [blame] | 2 | * Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved. |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #include <arch.h> |
| 8 | #include <asm_macros.S> |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 9 | #include <cortex_a75.h> |
Dimitris Papastamos | 1be747f | 2018-02-14 10:28:36 +0000 | [diff] [blame] | 10 | #include <cpuamu.h> |
| 11 | #include <cpu_macros.S> |
Dimitris Papastamos | d7e2e9e | 2017-12-11 11:45:35 +0000 | [diff] [blame] | 12 | |
John Tsichritzis | fe6df39 | 2019-03-19 17:20:52 +0000 | [diff] [blame] | 13 | /* Hardware handled coherency */ |
| 14 | #if HW_ASSISTED_COHERENCY == 0 |
| 15 | #error "Cortex-A75 must be compiled with HW_ASSISTED_COHERENCY enabled" |
| 16 | #endif |
| 17 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 18 | workaround_reset_start cortex_a75, ERRATUM(764081), ERRATA_A75_764081 |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 19 | sysreg_bit_set sctlr_el3, SCTLR_IESB_BIT |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 20 | workaround_reset_end cortex_a75, ERRATUM(764081) |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 21 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 22 | check_erratum_ls cortex_a75, ERRATUM(764081), CPU_REV(0, 0) |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 23 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 24 | workaround_reset_start cortex_a75, ERRATUM(790748), ERRATA_A75_790748 |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 25 | sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, (1 << 13) |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 26 | workaround_reset_end cortex_a75, ERRATUM(790748) |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 27 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 28 | check_erratum_ls cortex_a75, ERRATUM(790748), CPU_REV(0, 0) |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 29 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 30 | /* ERRATA_DSU_798953 : |
| 31 | * The errata is defined in dsu_helpers.S but applies to cortex_a75 |
| 32 | * as well. Henceforth creating symbolic names to the already existing errata |
| 33 | * workaround functions to get them registered under the Errata Framework. |
| 34 | */ |
| 35 | .equ check_erratum_cortex_a75_798953, check_errata_dsu_798953 |
| 36 | .equ erratum_cortex_a75_798953_wa, errata_dsu_798953_wa |
| 37 | add_erratum_entry cortex_a75, ERRATUM(798953), ERRATA_DSU_798953, APPLY_AT_RESET |
Louis Mayencourt | 78a0aed | 2019-02-20 12:11:41 +0000 | [diff] [blame] | 38 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 39 | /* ERRATA_DSU_936184 : |
| 40 | * The errata is defined in dsu_helpers.S but applies to cortex_a75 |
| 41 | * as well. Henceforth creating symbolic names to the already existing errata |
| 42 | * workaround functions to get them registered under the Errata Framework. |
| 43 | */ |
| 44 | .equ check_erratum_cortex_a75_936184, check_errata_dsu_936184 |
| 45 | .equ erratum_cortex_a75_936184_wa, errata_dsu_936184_wa |
| 46 | add_erratum_entry cortex_a75, ERRATUM(936184), ERRATA_DSU_936184, APPLY_AT_RESET |
Louis Mayencourt | 8d86870 | 2019-02-25 14:57:57 +0000 | [diff] [blame] | 47 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 48 | workaround_reset_start cortex_a75, CVE(2017, 5715), WORKAROUND_CVE_2017_5715 |
| 49 | #if IMAGE_BL31 |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 50 | override_vector_table wa_cve_2017_5715_bpiall_vbar |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 51 | #endif /* IMAGE_BL31 */ |
| 52 | workaround_reset_end cortex_a75, CVE(2017, 5715) |
| 53 | |
| 54 | check_erratum_custom_start cortex_a75, CVE(2017, 5715) |
| 55 | cpu_check_csv2 x0, 1f |
| 56 | #if WORKAROUND_CVE_2017_5715 |
| 57 | mov x0, #ERRATA_APPLIES |
| 58 | #else |
| 59 | mov x0, #ERRATA_MISSING |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 60 | #endif |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 61 | ret |
| 62 | 1: |
| 63 | mov x0, #ERRATA_NOT_APPLIES |
| 64 | ret |
| 65 | check_erratum_custom_end cortex_a75, CVE(2017, 5715) |
Dimitris Papastamos | c52ebdc | 2017-12-18 13:46:21 +0000 | [diff] [blame] | 66 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 67 | workaround_reset_start cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 68 | sysreg_bit_set CORTEX_A75_CPUACTLR_EL1, CORTEX_A75_CPUACTLR_EL1_DISABLE_LOAD_PASS_STORE |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 69 | workaround_reset_end cortex_a75, CVE(2018, 3639) |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 70 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 71 | check_erratum_chosen cortex_a75, CVE(2018, 3639), WORKAROUND_CVE_2018_3639 |
Louis Mayencourt | 4498b15 | 2019-04-09 16:29:01 +0100 | [diff] [blame] | 72 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 73 | workaround_reset_start cortex_a75, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 |
| 74 | #if IMAGE_BL31 |
| 75 | /* Skip installing vector table again if already done for CVE(2017, 5715) */ |
| 76 | adr x0, wa_cve_2017_5715_bpiall_vbar |
| 77 | mrs x1, vbar_el3 |
| 78 | cmp x0, x1 |
| 79 | b.eq 1f |
| 80 | msr vbar_el3, x0 |
| 81 | 1: |
| 82 | #endif /* IMAGE_BL31 */ |
| 83 | workaround_reset_end cortex_a75, CVE(2022, 23960) |
| 84 | |
| 85 | check_erratum_custom_start cortex_a75, CVE(2022, 23960) |
| 86 | #if WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 |
| 87 | cpu_check_csv2 x0, 1f |
| 88 | mov x0, #ERRATA_APPLIES |
| 89 | ret |
| 90 | 1: |
| 91 | # if WORKAROUND_CVE_2022_23960 |
| 92 | mov x0, #ERRATA_APPLIES |
| 93 | # else |
| 94 | mov x0, #ERRATA_MISSING |
| 95 | # endif /* WORKAROUND_CVE_2022_23960 */ |
| 96 | ret |
| 97 | #endif /* WORKAROUND_CVE_2017_5715 || WORKAROUND_CVE_2022_23960 */ |
| 98 | mov x0, #ERRATA_MISSING |
| 99 | ret |
| 100 | check_erratum_custom_end cortex_a75, CVE(2022, 23960) |
John Tsichritzis | 4daa1de | 2018-07-23 09:11:59 +0100 | [diff] [blame] | 101 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 102 | /* ------------------------------------------------- |
| 103 | * The CPU Ops reset function for Cortex-A75. |
| 104 | * ------------------------------------------------- |
| 105 | */ |
| 106 | |
| 107 | cpu_reset_func_start cortex_a75 |
Andre Przywara | 0b7f1b0 | 2023-03-21 13:53:19 +0000 | [diff] [blame] | 108 | #if ENABLE_FEAT_AMU |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 109 | /* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */ |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 110 | sysreg_bit_set actlr_el3, CORTEX_A75_ACTLR_AMEN_BIT |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 111 | isb |
| 112 | |
| 113 | /* Make sure accesses from EL0/EL1 are not trapped to EL2 */ |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 114 | sysreg_bit_set actlr_el2, CORTEX_A75_ACTLR_AMEN_BIT |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 115 | isb |
| 116 | |
| 117 | /* Enable group0 counters */ |
| 118 | mov x0, #CORTEX_A75_AMU_GROUP0_MASK |
| 119 | msr CPUAMCNTENSET_EL0, x0 |
| 120 | isb |
| 121 | |
| 122 | /* Enable group1 counters */ |
| 123 | mov x0, #CORTEX_A75_AMU_GROUP1_MASK |
| 124 | msr CPUAMCNTENSET_EL0, x0 |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 125 | /* isb included in cpu_reset_func_end macro */ |
Dimitris Papastamos | e6625ec | 2018-04-05 14:38:26 +0100 | [diff] [blame] | 126 | #endif |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 127 | cpu_reset_func_end cortex_a75 |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 128 | |
| 129 | func check_smccc_arch_workaround_3 |
| 130 | mov x0, #ERRATA_APPLIES |
| 131 | ret |
| 132 | endfunc check_smccc_arch_workaround_3 |
| 133 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 134 | /* --------------------------------------------- |
| 135 | * HW will do the cache maintenance while powering down |
| 136 | * --------------------------------------------- |
| 137 | */ |
| 138 | func cortex_a75_core_pwr_dwn |
| 139 | /* --------------------------------------------- |
| 140 | * Enable CPU power down bit in power control register |
| 141 | * --------------------------------------------- |
| 142 | */ |
Kathleen Capella | 65a3ce7 | 2023-06-09 14:11:53 -0400 | [diff] [blame] | 143 | sysreg_bit_set CORTEX_A75_CPUPWRCTLR_EL1, \ |
| 144 | CORTEX_A75_CORE_PWRDN_EN_MASK |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 145 | isb |
| 146 | ret |
| 147 | endfunc cortex_a75_core_pwr_dwn |
| 148 | |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 149 | errata_report_shim cortex_a75 |
Dimitris Papastamos | 858bd61 | 2018-01-16 10:32:47 +0000 | [diff] [blame] | 150 | |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 151 | /* --------------------------------------------- |
| 152 | * This function provides cortex_a75 specific |
| 153 | * register information for crash reporting. |
| 154 | * It needs to return with x6 pointing to |
| 155 | * a list of register names in ascii and |
| 156 | * x8 - x15 having values of registers to be |
| 157 | * reported. |
| 158 | * --------------------------------------------- |
| 159 | */ |
| 160 | .section .rodata.cortex_a75_regs, "aS" |
| 161 | cortex_a75_regs: /* The ascii list of register names to be reported */ |
| 162 | .asciz "cpuectlr_el1", "" |
| 163 | |
| 164 | func cortex_a75_cpu_reg_dump |
| 165 | adr x6, cortex_a75_regs |
| 166 | mrs x8, CORTEX_A75_CPUECTLR_EL1 |
| 167 | ret |
| 168 | endfunc cortex_a75_cpu_reg_dump |
| 169 | |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 170 | declare_cpu_ops_wa cortex_a75, CORTEX_A75_MIDR, \ |
Dimitris Papastamos | fcedb69 | 2017-10-16 11:40:10 +0100 | [diff] [blame] | 171 | cortex_a75_reset_func, \ |
Kathleen Capella | bd06ca2 | 2023-04-13 18:36:57 -0400 | [diff] [blame] | 172 | check_erratum_cortex_a75_5715, \ |
Dimitris Papastamos | ba51d9e | 2018-05-16 11:36:14 +0100 | [diff] [blame] | 173 | CPU_NO_EXTRA2_FUNC, \ |
Bipin Ravi | caa2e05 | 2022-02-23 23:45:50 -0600 | [diff] [blame] | 174 | check_smccc_arch_workaround_3, \ |
David Wang | 805c2c7 | 2016-11-09 16:29:02 +0000 | [diff] [blame] | 175 | cortex_a75_core_pwr_dwn |