Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 1 | /* |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 2 | * Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 5 | */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 6 | #ifndef ARM_DEF_H |
| 7 | #define ARM_DEF_H |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 8 | |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 9 | #include <arch.h> |
| 10 | #include <common/interrupt_props.h> |
| 11 | #include <common/tbbr/tbbr_img_def.h> |
| 12 | #include <drivers/arm/gic_common.h> |
| 13 | #include <lib/utils_def.h> |
| 14 | #include <lib/xlat_tables/xlat_tables_defs.h> |
Manish V Badarkhe | 5586151 | 2020-03-27 13:25:51 +0000 | [diff] [blame] | 15 | #include <plat/arm/common/smccc_def.h> |
Antonio Nino Diaz | e0f9063 | 2018-12-14 00:18:21 +0000 | [diff] [blame] | 16 | #include <plat/common/common_def.h> |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 17 | |
| 18 | /****************************************************************************** |
| 19 | * Definitions common to all ARM standard platforms |
| 20 | *****************************************************************************/ |
| 21 | |
Max Shvetsov | 06dba29 | 2019-12-06 11:50:12 +0000 | [diff] [blame] | 22 | /* |
| 23 | * Root of trust key hash lengths |
| 24 | */ |
| 25 | #define ARM_ROTPK_HEADER_LEN 19 |
| 26 | #define ARM_ROTPK_HASH_LEN 32 |
| 27 | |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 28 | /* Special value used to verify platform parameters from BL2 to BL31 */ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 29 | #define ARM_BL31_PLAT_PARAM_VAL ULL(0x0f1e2d3c4b5a6978) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 30 | |
Deepika Bhavnani | 4287c0c | 2019-12-13 10:23:18 -0600 | [diff] [blame] | 31 | #define ARM_SYSTEM_COUNT U(1) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 32 | |
| 33 | #define ARM_CACHE_WRITEBACK_SHIFT 6 |
| 34 | |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 35 | /* |
| 36 | * Macros mapping the MPIDR Affinity levels to ARM Platform Power levels. The |
| 37 | * power levels have a 1:1 mapping with the MPIDR affinity levels. |
| 38 | */ |
| 39 | #define ARM_PWR_LVL0 MPIDR_AFFLVL0 |
| 40 | #define ARM_PWR_LVL1 MPIDR_AFFLVL1 |
Soby Mathew | a869de1 | 2015-05-08 10:18:59 +0100 | [diff] [blame] | 41 | #define ARM_PWR_LVL2 MPIDR_AFFLVL2 |
Chandni Cherukuri | 9ec4a11 | 2018-10-16 14:42:19 +0530 | [diff] [blame] | 42 | #define ARM_PWR_LVL3 MPIDR_AFFLVL3 |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 43 | |
| 44 | /* |
| 45 | * Macros for local power states in ARM platforms encoded by State-ID field |
| 46 | * within the power-state parameter. |
| 47 | */ |
| 48 | /* Local power state for power domains in Run state. */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 49 | #define ARM_LOCAL_STATE_RUN U(0) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 50 | /* Local power state for retention. Valid only for CPU power domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 51 | #define ARM_LOCAL_STATE_RET U(1) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 52 | /* Local power state for OFF/power-down. Valid for CPU and cluster power |
| 53 | domains */ |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 54 | #define ARM_LOCAL_STATE_OFF U(2) |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 55 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 56 | /* Memory location options for TSP */ |
| 57 | #define ARM_TRUSTED_SRAM_ID 0 |
| 58 | #define ARM_TRUSTED_DRAM_ID 1 |
| 59 | #define ARM_DRAM_ID 2 |
| 60 | |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 61 | #ifdef PLAT_ARM_TRUSTED_SRAM_BASE |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 62 | #define ARM_TRUSTED_SRAM_BASE PLAT_ARM_TRUSTED_SRAM_BASE |
| 63 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 64 | #define ARM_TRUSTED_SRAM_BASE UL(0x04000000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 65 | #endif /* PLAT_ARM_TRUSTED_SRAM_BASE */ |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 66 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 67 | #define ARM_SHARED_RAM_BASE ARM_TRUSTED_SRAM_BASE |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 68 | #define ARM_SHARED_RAM_SIZE UL(0x00001000) /* 4 KB */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 69 | |
| 70 | /* The remaining Trusted SRAM is used to load the BL images */ |
| 71 | #define ARM_BL_RAM_BASE (ARM_SHARED_RAM_BASE + \ |
| 72 | ARM_SHARED_RAM_SIZE) |
| 73 | #define ARM_BL_RAM_SIZE (PLAT_ARM_TRUSTED_SRAM_SIZE - \ |
| 74 | ARM_SHARED_RAM_SIZE) |
| 75 | |
| 76 | /* |
| 77 | * The top 16MB of DRAM1 is configured as secure access only using the TZC |
| 78 | * - SCP TZC DRAM: If present, DRAM reserved for SCP use |
| 79 | * - AP TZC DRAM: The remaining TZC secured DRAM reserved for AP use |
| 80 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 81 | #define ARM_TZC_DRAM1_SIZE UL(0x01000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 82 | |
| 83 | #define ARM_SCP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 84 | ARM_DRAM1_SIZE - \ |
| 85 | ARM_SCP_TZC_DRAM1_SIZE) |
| 86 | #define ARM_SCP_TZC_DRAM1_SIZE PLAT_ARM_SCP_TZC_DRAM1_SIZE |
| 87 | #define ARM_SCP_TZC_DRAM1_END (ARM_SCP_TZC_DRAM1_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 88 | ARM_SCP_TZC_DRAM1_SIZE - 1U) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 89 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 90 | /* |
| 91 | * Define a 2MB region within the TZC secured DRAM for use by EL3 runtime |
| 92 | * firmware. This region is meant to be NOLOAD and will not be zero |
| 93 | * initialized. Data sections with the attribute `arm_el3_tzc_dram` will be |
| 94 | * placed here. |
| 95 | */ |
| 96 | #define ARM_EL3_TZC_DRAM1_BASE (ARM_SCP_TZC_DRAM1_BASE - ARM_EL3_TZC_DRAM1_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 97 | #define ARM_EL3_TZC_DRAM1_SIZE UL(0x00200000) /* 2 MB */ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 98 | #define ARM_EL3_TZC_DRAM1_END (ARM_EL3_TZC_DRAM1_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 99 | ARM_EL3_TZC_DRAM1_SIZE - 1U) |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 100 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 101 | #define ARM_AP_TZC_DRAM1_BASE (ARM_DRAM1_BASE + \ |
| 102 | ARM_DRAM1_SIZE - \ |
| 103 | ARM_TZC_DRAM1_SIZE) |
| 104 | #define ARM_AP_TZC_DRAM1_SIZE (ARM_TZC_DRAM1_SIZE - \ |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 105 | (ARM_SCP_TZC_DRAM1_SIZE + \ |
| 106 | ARM_EL3_TZC_DRAM1_SIZE)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 107 | #define ARM_AP_TZC_DRAM1_END (ARM_AP_TZC_DRAM1_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 108 | ARM_AP_TZC_DRAM1_SIZE - 1U) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 109 | |
Soby Mathew | 7e4d665 | 2017-05-10 11:50:30 +0100 | [diff] [blame] | 110 | /* Define the Access permissions for Secure peripherals to NS_DRAM */ |
| 111 | #if ARM_CRYPTOCELL_INTEG |
| 112 | /* |
| 113 | * Allow Secure peripheral to read NS DRAM when integrated with CryptoCell. |
| 114 | * This is required by CryptoCell to authenticate BL33 which is loaded |
| 115 | * into the Non Secure DDR. |
| 116 | */ |
| 117 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_RD |
| 118 | #else |
| 119 | #define ARM_TZC_NS_DRAM_S_ACCESS TZC_REGION_S_NONE |
| 120 | #endif |
| 121 | |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 122 | #ifdef SPD_opteed |
| 123 | /* |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 124 | * BL2 needs to map 4MB at the end of TZC_DRAM1 in order to |
| 125 | * load/authenticate the trusted os extra image. The first 512KB of |
| 126 | * TZC_DRAM1 are reserved for trusted os (OPTEE). The extra image loading |
| 127 | * for OPTEE is paged image which only include the paging part using |
| 128 | * virtual memory but without "init" data. OPTEE will copy the "init" data |
| 129 | * (from pager image) to the first 512KB of TZC_DRAM, and then copy the |
| 130 | * extra image behind the "init" data. |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 131 | */ |
Jens Wiklander | ae73b16 | 2017-08-24 15:39:09 +0200 | [diff] [blame] | 132 | #define ARM_OPTEE_PAGEABLE_LOAD_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
| 133 | ARM_AP_TZC_DRAM1_SIZE - \ |
| 134 | ARM_OPTEE_PAGEABLE_LOAD_SIZE) |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 135 | #define ARM_OPTEE_PAGEABLE_LOAD_SIZE UL(0x400000) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 136 | #define ARM_OPTEE_PAGEABLE_LOAD_MEM MAP_REGION_FLAT( \ |
| 137 | ARM_OPTEE_PAGEABLE_LOAD_BASE, \ |
| 138 | ARM_OPTEE_PAGEABLE_LOAD_SIZE, \ |
| 139 | MT_MEMORY | MT_RW | MT_SECURE) |
Soby Mathew | 874fc9e | 2017-09-01 13:43:50 +0100 | [diff] [blame] | 140 | |
| 141 | /* |
| 142 | * Map the memory for the OP-TEE core (also known as OP-TEE pager when paging |
| 143 | * support is enabled). |
| 144 | */ |
| 145 | #define ARM_MAP_OPTEE_CORE_MEM MAP_REGION_FLAT( \ |
| 146 | BL32_BASE, \ |
| 147 | BL32_LIMIT - BL32_BASE, \ |
| 148 | MT_MEMORY | MT_RW | MT_SECURE) |
Summer Qin | 9db8f2e | 2017-04-24 16:49:28 +0100 | [diff] [blame] | 149 | #endif /* SPD_opteed */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 150 | |
| 151 | #define ARM_NS_DRAM1_BASE ARM_DRAM1_BASE |
| 152 | #define ARM_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \ |
| 153 | ARM_TZC_DRAM1_SIZE) |
| 154 | #define ARM_NS_DRAM1_END (ARM_NS_DRAM1_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 155 | ARM_NS_DRAM1_SIZE - 1U) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 156 | #ifdef PLAT_ARM_DRAM1_BASE |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 157 | #define ARM_DRAM1_BASE PLAT_ARM_DRAM1_BASE |
| 158 | #else |
Sandrine Bailleux | 6c32fc7 | 2018-10-31 14:28:17 +0100 | [diff] [blame] | 159 | #define ARM_DRAM1_BASE ULL(0x80000000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 160 | #endif /* PLAT_ARM_DRAM1_BASE */ |
laurenw-arm | 7c7b198 | 2020-10-21 13:34:40 -0500 | [diff] [blame] | 161 | |
Sandrine Bailleux | 6c32fc7 | 2018-10-31 14:28:17 +0100 | [diff] [blame] | 162 | #define ARM_DRAM1_SIZE ULL(0x80000000) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 163 | #define ARM_DRAM1_END (ARM_DRAM1_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 164 | ARM_DRAM1_SIZE - 1U) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 165 | |
Sami Mujawar | a43ae7c | 2019-05-09 13:35:02 +0100 | [diff] [blame] | 166 | #define ARM_DRAM2_BASE PLAT_ARM_DRAM2_BASE |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 167 | #define ARM_DRAM2_SIZE PLAT_ARM_DRAM2_SIZE |
| 168 | #define ARM_DRAM2_END (ARM_DRAM2_BASE + \ |
Alexei Fedorov | c717617 | 2020-07-13 12:11:05 +0100 | [diff] [blame] | 169 | ARM_DRAM2_SIZE - 1U) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 170 | |
| 171 | #define ARM_IRQ_SEC_PHY_TIMER 29 |
| 172 | |
| 173 | #define ARM_IRQ_SEC_SGI_0 8 |
| 174 | #define ARM_IRQ_SEC_SGI_1 9 |
| 175 | #define ARM_IRQ_SEC_SGI_2 10 |
| 176 | #define ARM_IRQ_SEC_SGI_3 11 |
| 177 | #define ARM_IRQ_SEC_SGI_4 12 |
| 178 | #define ARM_IRQ_SEC_SGI_5 13 |
| 179 | #define ARM_IRQ_SEC_SGI_6 14 |
| 180 | #define ARM_IRQ_SEC_SGI_7 15 |
| 181 | |
Achin Gupta | 1fa7eb6 | 2015-11-03 14:18:34 +0000 | [diff] [blame] | 182 | /* |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 183 | * Define a list of Group 1 Secure and Group 0 interrupt properties as per GICv3 |
| 184 | * terminology. On a GICv2 system or mode, the lists will be merged and treated |
| 185 | * as Group 0 interrupts. |
| 186 | */ |
| 187 | #define ARM_G1S_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 188 | INTR_PROP_DESC(ARM_IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 189 | GIC_INTR_CFG_LEVEL), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 190 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 191 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 192 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 193 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 194 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 195 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 196 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 197 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 198 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 199 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 200 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 201 | GIC_INTR_CFG_EDGE) |
| 202 | |
| 203 | #define ARM_G0_IRQ_PROPS(grp) \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 204 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_0, PLAT_SDEI_NORMAL_PRI, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 205 | GIC_INTR_CFG_EDGE), \ |
Antonio Nino Diaz | e590fd5 | 2018-08-21 09:42:26 +0100 | [diff] [blame] | 206 | INTR_PROP_DESC(ARM_IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY, (grp), \ |
Jeenu Viswambharan | 723dce0 | 2017-09-22 08:59:59 +0100 | [diff] [blame] | 207 | GIC_INTR_CFG_EDGE) |
| 208 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 209 | #define ARM_MAP_SHARED_RAM MAP_REGION_FLAT( \ |
| 210 | ARM_SHARED_RAM_BASE, \ |
| 211 | ARM_SHARED_RAM_SIZE, \ |
Juan Castillo | 2e86cb1 | 2016-01-13 15:01:09 +0000 | [diff] [blame] | 212 | MT_DEVICE | MT_RW | MT_SECURE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 213 | |
| 214 | #define ARM_MAP_NS_DRAM1 MAP_REGION_FLAT( \ |
| 215 | ARM_NS_DRAM1_BASE, \ |
| 216 | ARM_NS_DRAM1_SIZE, \ |
| 217 | MT_MEMORY | MT_RW | MT_NS) |
| 218 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 219 | #define ARM_MAP_DRAM2 MAP_REGION_FLAT( \ |
| 220 | ARM_DRAM2_BASE, \ |
| 221 | ARM_DRAM2_SIZE, \ |
| 222 | MT_MEMORY | MT_RW | MT_NS) |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 223 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 224 | #define ARM_MAP_TSP_SEC_MEM MAP_REGION_FLAT( \ |
| 225 | TSP_SEC_MEM_BASE, \ |
| 226 | TSP_SEC_MEM_SIZE, \ |
| 227 | MT_MEMORY | MT_RW | MT_SECURE) |
| 228 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 229 | #if ARM_BL31_IN_DRAM |
| 230 | #define ARM_MAP_BL31_SEC_DRAM MAP_REGION_FLAT( \ |
| 231 | BL31_BASE, \ |
| 232 | PLAT_ARM_MAX_BL31_SIZE, \ |
| 233 | MT_MEMORY | MT_RW | MT_SECURE) |
| 234 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 235 | |
Soby Mathew | 3b5156e | 2017-10-05 12:27:33 +0100 | [diff] [blame] | 236 | #define ARM_MAP_EL3_TZC_DRAM MAP_REGION_FLAT( \ |
| 237 | ARM_EL3_TZC_DRAM1_BASE, \ |
| 238 | ARM_EL3_TZC_DRAM1_SIZE, \ |
| 239 | MT_MEMORY | MT_RW | MT_SECURE) |
| 240 | |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 241 | #if defined(SPD_spmd) |
| 242 | #define ARM_MAP_TRUSTED_DRAM MAP_REGION_FLAT( \ |
| 243 | PLAT_ARM_TRUSTED_DRAM_BASE, \ |
| 244 | PLAT_ARM_TRUSTED_DRAM_SIZE, \ |
| 245 | MT_MEMORY | MT_RW | MT_SECURE) |
| 246 | #endif |
| 247 | |
| 248 | |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 249 | /* |
John Tsichritzis | c34341a | 2018-07-30 13:41:52 +0100 | [diff] [blame] | 250 | * Mapping for the BL1 RW region. This mapping is needed by BL2 in order to |
| 251 | * share the Mbed TLS heap. Since the heap is allocated inside BL1, it resides |
| 252 | * in the BL1 RW region. Hence, BL2 needs access to the BL1 RW region in order |
| 253 | * to be able to access the heap. |
| 254 | */ |
| 255 | #define ARM_MAP_BL1_RW MAP_REGION_FLAT( \ |
| 256 | BL1_RW_BASE, \ |
| 257 | BL1_RW_LIMIT - BL1_RW_BASE, \ |
| 258 | MT_MEMORY | MT_RW | MT_SECURE) |
| 259 | |
| 260 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 261 | * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section |
| 262 | * otherwise one region is defined containing both. |
| 263 | */ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 264 | #if SEPARATE_CODE_AND_RODATA |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 265 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 266 | BL_CODE_BASE, \ |
| 267 | BL_CODE_END - BL_CODE_BASE, \ |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 268 | MT_CODE | MT_SECURE), \ |
| 269 | MAP_REGION_FLAT( \ |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 270 | BL_RO_DATA_BASE, \ |
| 271 | BL_RO_DATA_END \ |
| 272 | - BL_RO_DATA_BASE, \ |
| 273 | MT_RO_DATA | MT_SECURE) |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 274 | #else |
| 275 | #define ARM_MAP_BL_RO MAP_REGION_FLAT( \ |
| 276 | BL_CODE_BASE, \ |
| 277 | BL_CODE_END - BL_CODE_BASE, \ |
| 278 | MT_CODE | MT_SECURE) |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 279 | #endif |
| 280 | #if USE_COHERENT_MEM |
| 281 | #define ARM_MAP_BL_COHERENT_RAM MAP_REGION_FLAT( \ |
| 282 | BL_COHERENT_RAM_BASE, \ |
| 283 | BL_COHERENT_RAM_END \ |
| 284 | - BL_COHERENT_RAM_BASE, \ |
| 285 | MT_DEVICE | MT_RW | MT_SECURE) |
| 286 | #endif |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 287 | #if USE_ROMLIB |
| 288 | #define ARM_MAP_ROMLIB_CODE MAP_REGION_FLAT( \ |
| 289 | ROMLIB_RO_BASE, \ |
| 290 | ROMLIB_RO_LIMIT - ROMLIB_RO_BASE,\ |
| 291 | MT_CODE | MT_SECURE) |
| 292 | |
| 293 | #define ARM_MAP_ROMLIB_DATA MAP_REGION_FLAT( \ |
| 294 | ROMLIB_RW_BASE, \ |
| 295 | ROMLIB_RW_END - ROMLIB_RW_BASE,\ |
| 296 | MT_MEMORY | MT_RW | MT_SECURE) |
| 297 | #endif |
Daniel Boulby | 45a2c9e | 2018-07-06 16:54:44 +0100 | [diff] [blame] | 298 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 299 | /* |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 300 | * Map mem_protect flash region with read and write permissions |
| 301 | */ |
| 302 | #define ARM_V2M_MAP_MEM_PROTECT MAP_REGION_FLAT(PLAT_ARM_MEM_PROT_ADDR, \ |
| 303 | V2M_FLASH_BLOCK_SIZE, \ |
| 304 | MT_DEVICE | MT_RW | MT_SECURE) |
Manish V Badarkhe | 5e3ef6c | 2020-07-16 05:45:25 +0100 | [diff] [blame] | 305 | /* |
| 306 | * Map the region for device tree configuration with read and write permissions |
| 307 | */ |
| 308 | #define ARM_MAP_BL_CONFIG_REGION MAP_REGION_FLAT(ARM_BL_RAM_BASE, \ |
| 309 | (ARM_FW_CONFIGS_LIMIT \ |
| 310 | - ARM_BL_RAM_BASE), \ |
| 311 | MT_MEMORY | MT_RW | MT_SECURE) |
Antonio Nino Diaz | 48bfb54 | 2018-10-11 13:02:34 +0100 | [diff] [blame] | 312 | |
| 313 | /* |
Daniel Boulby | 4e97abd | 2018-07-16 14:09:15 +0100 | [diff] [blame] | 314 | * The max number of regions like RO(code), coherent and data required by |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 315 | * different BL stages which need to be mapped in the MMU. |
| 316 | */ |
Manish V Badarkhe | 5e3ef6c | 2020-07-16 05:45:25 +0100 | [diff] [blame] | 317 | #define ARM_BL_REGIONS 6 |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 318 | |
| 319 | #define MAX_MMAP_REGIONS (PLAT_ARM_MMAP_ENTRIES + \ |
| 320 | ARM_BL_REGIONS) |
| 321 | |
| 322 | /* Memory mapped Generic timer interfaces */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 323 | #ifdef PLAT_ARM_SYS_CNTCTL_BASE |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 324 | #define ARM_SYS_CNTCTL_BASE PLAT_ARM_SYS_CNTCTL_BASE |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 325 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 326 | #define ARM_SYS_CNTCTL_BASE UL(0x2a430000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 327 | #endif |
| 328 | |
| 329 | #ifdef PLAT_ARM_SYS_CNTREAD_BASE |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 330 | #define ARM_SYS_CNTREAD_BASE PLAT_ARM_SYS_CNTREAD_BASE |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 331 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 332 | #define ARM_SYS_CNTREAD_BASE UL(0x2a800000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 333 | #endif |
| 334 | |
| 335 | #ifdef PLAT_ARM_SYS_TIMCTL_BASE |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 336 | #define ARM_SYS_TIMCTL_BASE PLAT_ARM_SYS_TIMCTL_BASE |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 337 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 338 | #define ARM_SYS_TIMCTL_BASE UL(0x2a810000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 339 | #endif |
| 340 | |
| 341 | #ifdef PLAT_ARM_SYS_CNT_BASE_S |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 342 | #define ARM_SYS_CNT_BASE_S PLAT_ARM_SYS_CNT_BASE_S |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 343 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 344 | #define ARM_SYS_CNT_BASE_S UL(0x2a820000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 345 | #endif |
| 346 | |
| 347 | #ifdef PLAT_ARM_SYS_CNT_BASE_NS |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 348 | #define ARM_SYS_CNT_BASE_NS PLAT_ARM_SYS_CNT_BASE_NS |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 349 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 350 | #define ARM_SYS_CNT_BASE_NS UL(0x2a830000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 351 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 352 | |
| 353 | #define ARM_CONSOLE_BAUDRATE 115200 |
| 354 | |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 355 | /* Trusted Watchdog constants */ |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 356 | #ifdef PLAT_ARM_SP805_TWDG_BASE |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 357 | #define ARM_SP805_TWDG_BASE PLAT_ARM_SP805_TWDG_BASE |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 358 | #else |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 359 | #define ARM_SP805_TWDG_BASE UL(0x2a490000) |
Gary Morrison | 3d7f654 | 2021-01-27 13:08:47 -0600 | [diff] [blame] | 360 | #endif |
Juan Castillo | b6132f1 | 2015-10-06 14:01:35 +0100 | [diff] [blame] | 361 | #define ARM_SP805_TWDG_CLK_HZ 32768 |
| 362 | /* The TBBR document specifies a watchdog timeout of 256 seconds. SP805 |
| 363 | * asserts reset after two consecutive countdowns (2 x 128 = 256 sec) */ |
| 364 | #define ARM_TWDG_TIMEOUT_SEC 128 |
| 365 | #define ARM_TWDG_LOAD_VAL (ARM_SP805_TWDG_CLK_HZ * \ |
| 366 | ARM_TWDG_TIMEOUT_SEC) |
| 367 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 368 | /****************************************************************************** |
| 369 | * Required platform porting definitions common to all ARM standard platforms |
| 370 | *****************************************************************************/ |
| 371 | |
Roberto Vargas | f8fda10 | 2017-08-08 11:27:20 +0100 | [diff] [blame] | 372 | /* |
Soby Mathew | fec4eb7 | 2015-07-01 16:16:20 +0100 | [diff] [blame] | 373 | * This macro defines the deepest retention state possible. A higher state |
| 374 | * id will represent an invalid or a power down state. |
| 375 | */ |
| 376 | #define PLAT_MAX_RET_STATE ARM_LOCAL_STATE_RET |
| 377 | |
| 378 | /* |
| 379 | * This macro defines the deepest power down states possible. Any state ID |
| 380 | * higher than this is invalid. |
| 381 | */ |
| 382 | #define PLAT_MAX_OFF_STATE ARM_LOCAL_STATE_OFF |
| 383 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 384 | /* |
| 385 | * Some data must be aligned on the biggest cache line size in the platform. |
| 386 | * This is known only to the platform as it might have a combination of |
| 387 | * integrated and external caches. |
| 388 | */ |
Antonio Nino Diaz | 5f47579 | 2018-10-15 14:58:11 +0100 | [diff] [blame] | 389 | #define CACHE_WRITEBACK_GRANULE (U(1) << ARM_CACHE_WRITEBACK_SHIFT) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 390 | |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 391 | /* |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 392 | * To enable FW_CONFIG to be loaded by BL1, define the corresponding base |
Soby Mathew | 7c6df5b | 2018-01-15 14:43:42 +0000 | [diff] [blame] | 393 | * and limit. Leave enough space of BL2 meminfo. |
| 394 | */ |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 395 | #define ARM_FW_CONFIG_BASE (ARM_BL_RAM_BASE + sizeof(meminfo_t)) |
Manish V Badarkhe | 0bafa82 | 2020-06-29 11:14:07 +0100 | [diff] [blame] | 396 | #define ARM_FW_CONFIG_LIMIT ((ARM_BL_RAM_BASE + PAGE_SIZE) \ |
| 397 | + (PAGE_SIZE / 2U)) |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 398 | |
| 399 | /* |
| 400 | * Boot parameters passed from BL2 to BL31/BL32 are stored here |
| 401 | */ |
Manish V Badarkhe | 0bafa82 | 2020-06-29 11:14:07 +0100 | [diff] [blame] | 402 | #define ARM_BL2_MEM_DESC_BASE (ARM_FW_CONFIG_LIMIT) |
| 403 | #define ARM_BL2_MEM_DESC_LIMIT (ARM_BL2_MEM_DESC_BASE \ |
| 404 | + (PAGE_SIZE / 2U)) |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 405 | |
| 406 | /* |
| 407 | * Define limit of firmware configuration memory: |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 408 | * ARM_FW_CONFIG + ARM_BL2_MEM_DESC memory |
Sathees Balya | 9095009 | 2018-11-15 14:22:30 +0000 | [diff] [blame] | 409 | */ |
Manish V Badarkhe | fbf1fd2 | 2020-06-09 11:31:17 +0100 | [diff] [blame] | 410 | #define ARM_FW_CONFIGS_LIMIT (ARM_BL_RAM_BASE + (PAGE_SIZE * 2)) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 411 | |
| 412 | /******************************************************************************* |
| 413 | * BL1 specific defines. |
| 414 | * BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of |
| 415 | * addresses. |
| 416 | ******************************************************************************/ |
| 417 | #define BL1_RO_BASE PLAT_ARM_TRUSTED_ROM_BASE |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 418 | #ifdef PLAT_BL1_RO_LIMIT |
| 419 | #define BL1_RO_LIMIT PLAT_BL1_RO_LIMIT |
| 420 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 421 | #define BL1_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 422 | + (PLAT_ARM_TRUSTED_ROM_SIZE - \ |
| 423 | PLAT_ARM_MAX_ROMLIB_RO_SIZE)) |
laurenw-arm | 56f1e3e | 2021-03-03 14:19:38 -0600 | [diff] [blame] | 424 | #endif |
| 425 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 426 | /* |
Vikram Kanigiri | 5d86f2e | 2016-01-21 14:08:15 +0000 | [diff] [blame] | 427 | * Put BL1 RW at the top of the Trusted SRAM. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 428 | */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 429 | #define BL1_RW_BASE (ARM_BL_RAM_BASE + \ |
| 430 | ARM_BL_RAM_SIZE - \ |
Roberto Vargas | e3adc37 | 2018-05-23 09:27:06 +0100 | [diff] [blame] | 431 | (PLAT_ARM_MAX_BL1_RW_SIZE +\ |
| 432 | PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 433 | #define BL1_RW_LIMIT (ARM_BL_RAM_BASE + \ |
| 434 | (ARM_BL_RAM_SIZE - PLAT_ARM_MAX_ROMLIB_RW_SIZE)) |
| 435 | |
| 436 | #define ROMLIB_RO_BASE BL1_RO_LIMIT |
| 437 | #define ROMLIB_RO_LIMIT (PLAT_ARM_TRUSTED_ROM_BASE + PLAT_ARM_TRUSTED_ROM_SIZE) |
| 438 | |
| 439 | #define ROMLIB_RW_BASE (BL1_RW_BASE + PLAT_ARM_MAX_BL1_RW_SIZE) |
| 440 | #define ROMLIB_RW_END (ROMLIB_RW_BASE + PLAT_ARM_MAX_ROMLIB_RW_SIZE) |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 441 | |
| 442 | /******************************************************************************* |
| 443 | * BL2 specific defines. |
| 444 | ******************************************************************************/ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 445 | #if BL2_AT_EL3 |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 446 | /* Put BL2 towards the middle of the Trusted SRAM */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 447 | #define BL2_BASE (ARM_TRUSTED_SRAM_BASE + \ |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 448 | (PLAT_ARM_TRUSTED_SRAM_SIZE >> 1) + 0x2000) |
Roberto Vargas | 5220780 | 2017-11-17 13:22:18 +0000 | [diff] [blame] | 449 | #define BL2_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 450 | |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 451 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 452 | /* |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 453 | * Put BL2 just below BL1. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 454 | */ |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 455 | #define BL2_BASE (BL1_RW_BASE - PLAT_ARM_MAX_BL2_SIZE) |
| 456 | #define BL2_LIMIT BL1_RW_BASE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 457 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 458 | |
| 459 | /******************************************************************************* |
Juan Castillo | 7d19941 | 2015-12-14 09:35:25 +0000 | [diff] [blame] | 460 | * BL31 specific defines. |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 461 | ******************************************************************************/ |
Madhukar Pappireddy | d741944 | 2020-01-27 15:38:26 -0600 | [diff] [blame] | 462 | #if ARM_BL31_IN_DRAM || SEPARATE_NOBITS_REGION |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 463 | /* |
| 464 | * Put BL31 at the bottom of TZC secured DRAM |
| 465 | */ |
| 466 | #define BL31_BASE ARM_AP_TZC_DRAM1_BASE |
| 467 | #define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
| 468 | PLAT_ARM_MAX_BL31_SIZE) |
Madhukar Pappireddy | d741944 | 2020-01-27 15:38:26 -0600 | [diff] [blame] | 469 | /* |
| 470 | * For SEPARATE_NOBITS_REGION, BL31 PROGBITS are loaded in TZC secured DRAM. |
| 471 | * And BL31 NOBITS are loaded in Trusted SRAM such that BL2 is overwritten. |
| 472 | */ |
| 473 | #if SEPARATE_NOBITS_REGION |
| 474 | #define BL31_NOBITS_BASE BL2_BASE |
| 475 | #define BL31_NOBITS_LIMIT BL2_LIMIT |
| 476 | #endif /* SEPARATE_NOBITS_REGION */ |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 477 | #elif (RESET_TO_BL31) |
Manish Pandey | 2207e93 | 2019-11-06 13:17:46 +0000 | [diff] [blame] | 478 | /* Ensure Position Independent support (PIE) is enabled for this config.*/ |
| 479 | # if !ENABLE_PIE |
| 480 | # error "BL31 must be a PIE if RESET_TO_BL31=1." |
| 481 | #endif |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 482 | /* |
Soby Mathew | 68e6928 | 2018-12-12 14:13:52 +0000 | [diff] [blame] | 483 | * Since this is PIE, we can define BL31_BASE to 0x0 since this macro is solely |
Soby Mathew | c5e1745 | 2019-01-07 14:07:58 +0000 | [diff] [blame] | 484 | * used for building BL31 and not used for loading BL31. |
Qixiang Xu | a5f7281 | 2017-08-31 11:45:32 +0800 | [diff] [blame] | 485 | */ |
Soby Mathew | c5e1745 | 2019-01-07 14:07:58 +0000 | [diff] [blame] | 486 | # define BL31_BASE 0x0 |
| 487 | # define BL31_LIMIT PLAT_ARM_MAX_BL31_SIZE |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 488 | #else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 489 | /* Put BL31 below BL2 in the Trusted SRAM.*/ |
| 490 | #define BL31_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 491 | - PLAT_ARM_MAX_BL31_SIZE) |
| 492 | #define BL31_PROGBITS_LIMIT BL2_BASE |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 493 | /* |
| 494 | * For BL2_AT_EL3 make sure the BL31 can grow up until BL2_BASE. This is |
| 495 | * because in the BL2_AT_EL3 configuration, BL2 is always resident. |
| 496 | */ |
| 497 | #if BL2_AT_EL3 |
| 498 | #define BL31_LIMIT BL2_BASE |
| 499 | #else |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 500 | #define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 501 | #endif |
Dimitris Papastamos | 2583649 | 2018-06-11 11:07:58 +0100 | [diff] [blame] | 502 | #endif |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 503 | |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 504 | #if !defined(__aarch64__) || JUNO_AARCH32_EL3_RUNTIME |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 505 | /******************************************************************************* |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 506 | * BL32 specific defines for EL3 runtime in AArch32 mode |
| 507 | ******************************************************************************/ |
| 508 | # if RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 509 | /* Ensure Position Independent support (PIE) is enabled for this config.*/ |
| 510 | # if !ENABLE_PIE |
| 511 | # error "BL32 must be a PIE if RESET_TO_SP_MIN=1." |
| 512 | #endif |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 513 | /* |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 514 | * Since this is PIE, we can define BL32_BASE to 0x0 since this macro is solely |
| 515 | * used for building BL32 and not used for loading BL32. |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 516 | */ |
Manish Pandey | 928da86 | 2021-06-10 15:22:48 +0100 | [diff] [blame] | 517 | # define BL32_BASE 0x0 |
| 518 | # define BL32_LIMIT PLAT_ARM_MAX_BL32_SIZE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 519 | # else |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 520 | /* Put BL32 below BL2 in the Trusted SRAM.*/ |
| 521 | # define BL32_BASE ((ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)\ |
| 522 | - PLAT_ARM_MAX_BL32_SIZE) |
| 523 | # define BL32_PROGBITS_LIMIT BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 524 | # define BL32_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE) |
| 525 | # endif /* RESET_TO_SP_MIN && !JUNO_AARCH32_EL3_RUNTIME */ |
| 526 | |
| 527 | #else |
| 528 | /******************************************************************************* |
| 529 | * BL32 specific defines for EL3 runtime in AArch64 mode |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 530 | ******************************************************************************/ |
| 531 | /* |
| 532 | * On ARM standard platforms, the TSP can execute from Trusted SRAM, |
| 533 | * Trusted DRAM (if available) or the DRAM region secured by the TrustZone |
| 534 | * controller. |
| 535 | */ |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 536 | # if SPM_MM |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 537 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 538 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
| 539 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 540 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 541 | ARM_AP_TZC_DRAM1_SIZE) |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 542 | # elif defined(SPD_spmd) |
| 543 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + ULL(0x200000)) |
| 544 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - ULL(0x200000)) |
Arunachalam Ganapathy | 40618cf | 2020-07-27 13:51:30 +0100 | [diff] [blame] | 545 | # define BL32_BASE PLAT_ARM_SPMC_BASE |
| 546 | # define BL32_LIMIT (PLAT_ARM_SPMC_BASE + \ |
| 547 | PLAT_ARM_SPMC_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 548 | # elif ARM_BL31_IN_DRAM |
| 549 | # define TSP_SEC_MEM_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 550 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 551 | # define TSP_SEC_MEM_SIZE (ARM_AP_TZC_DRAM1_SIZE - \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 552 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 553 | # define BL32_BASE (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 554 | PLAT_ARM_MAX_BL31_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 555 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
David Wang | 0ba499f | 2016-03-07 11:02:57 +0800 | [diff] [blame] | 556 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 557 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_SRAM_ID |
| 558 | # define TSP_SEC_MEM_BASE ARM_BL_RAM_BASE |
| 559 | # define TSP_SEC_MEM_SIZE ARM_BL_RAM_SIZE |
Soby Mathew | af14b46 | 2018-06-01 16:53:38 +0100 | [diff] [blame] | 560 | # define TSP_PROGBITS_LIMIT BL31_BASE |
Manish V Badarkhe | 1da211a | 2020-05-31 10:17:59 +0100 | [diff] [blame] | 561 | # define BL32_BASE ARM_FW_CONFIGS_LIMIT |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 562 | # define BL32_LIMIT BL31_BASE |
| 563 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_TRUSTED_DRAM_ID |
| 564 | # define TSP_SEC_MEM_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 565 | # define TSP_SEC_MEM_SIZE PLAT_ARM_TRUSTED_DRAM_SIZE |
| 566 | # define BL32_BASE PLAT_ARM_TRUSTED_DRAM_BASE |
| 567 | # define BL32_LIMIT (PLAT_ARM_TRUSTED_DRAM_BASE \ |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 568 | + (UL(1) << 21)) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 569 | # elif ARM_TSP_RAM_LOCATION_ID == ARM_DRAM_ID |
| 570 | # define TSP_SEC_MEM_BASE ARM_AP_TZC_DRAM1_BASE |
| 571 | # define TSP_SEC_MEM_SIZE ARM_AP_TZC_DRAM1_SIZE |
| 572 | # define BL32_BASE ARM_AP_TZC_DRAM1_BASE |
| 573 | # define BL32_LIMIT (ARM_AP_TZC_DRAM1_BASE + \ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 574 | ARM_AP_TZC_DRAM1_SIZE) |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 575 | # else |
| 576 | # error "Unsupported ARM_TSP_RAM_LOCATION_ID value" |
| 577 | # endif |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 578 | #endif /* !__aarch64__ || JUNO_AARCH32_EL3_RUNTIME */ |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 579 | |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 580 | /* |
| 581 | * BL32 is mandatory in AArch32. In AArch64, undefine BL32_BASE if there is no |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 582 | * SPD and no SPM-MM, as they are the only ones that can be used as BL32. |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 583 | */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 584 | #if defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME |
Paul Beesley | db4e25a | 2019-10-14 15:27:12 +0000 | [diff] [blame] | 585 | # if defined(SPD_none) && !SPM_MM |
Antonio Nino Diaz | 7289f92 | 2017-11-09 11:34:09 +0000 | [diff] [blame] | 586 | # undef BL32_BASE |
Achin Gupta | e97351d | 2019-10-11 15:15:19 +0100 | [diff] [blame] | 587 | # endif /* defined(SPD_none) && !SPM_MM */ |
Julius Werner | 8e0ef0f | 2019-07-09 14:02:43 -0700 | [diff] [blame] | 588 | #endif /* defined(__aarch64__) && !JUNO_AARCH32_EL3_RUNTIME */ |
Antonio Nino Diaz | e4fa370 | 2016-04-05 11:38:49 +0100 | [diff] [blame] | 589 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 590 | /******************************************************************************* |
| 591 | * FWU Images: NS_BL1U, BL2U & NS_BL2U defines. |
| 592 | ******************************************************************************/ |
| 593 | #define BL2U_BASE BL2_BASE |
Soby Mathew | bf16923 | 2017-11-14 14:10:10 +0000 | [diff] [blame] | 594 | #define BL2U_LIMIT BL2_LIMIT |
| 595 | |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 596 | #define NS_BL2U_BASE ARM_NS_DRAM1_BASE |
Antonio Nino Diaz | ab5d2b1 | 2018-10-30 16:12:32 +0000 | [diff] [blame] | 597 | #define NS_BL1U_BASE (PLAT_ARM_NVM_BASE + UL(0x03EB8000)) |
Yatharth Kochar | 736a3bf | 2015-10-11 14:14:55 +0100 | [diff] [blame] | 598 | |
Dan Handley | 9df4804 | 2015-03-19 18:58:55 +0000 | [diff] [blame] | 599 | /* |
| 600 | * ID of the secure physical generic timer interrupt used by the TSP. |
| 601 | */ |
| 602 | #define TSP_IRQ_SEC_PHY_TIMER ARM_IRQ_SEC_PHY_TIMER |
| 603 | |
| 604 | |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 605 | /* |
| 606 | * One cache line needed for bakery locks on ARM platforms |
| 607 | */ |
| 608 | #define PLAT_PERCPU_BAKERY_LOCK_SIZE (1 * CACHE_WRITEBACK_GRANULE) |
| 609 | |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 610 | /* Priority levels for ARM platforms */ |
Jeenu Viswambharan | a5b5b8d | 2018-02-06 12:21:39 +0000 | [diff] [blame] | 611 | #define PLAT_RAS_PRI 0x10 |
Jeenu Viswambharan | b183745 | 2017-10-24 11:47:13 +0100 | [diff] [blame] | 612 | #define PLAT_SDEI_CRITICAL_PRI 0x60 |
| 613 | #define PLAT_SDEI_NORMAL_PRI 0x70 |
| 614 | |
| 615 | /* ARM platforms use 3 upper bits of secure interrupt priority */ |
Sandeep Tripathy | 1c47839 | 2020-08-12 18:42:13 +0530 | [diff] [blame] | 616 | #define PLAT_PRI_BITS 3 |
Vikram Kanigiri | d79214c | 2015-09-09 10:52:13 +0100 | [diff] [blame] | 617 | |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 618 | /* SGI used for SDEI signalling */ |
| 619 | #define ARM_SDEI_SGI ARM_IRQ_SEC_SGI_0 |
| 620 | |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 621 | #if SDEI_IN_FCONF |
| 622 | /* ARM SDEI dynamic private event max count */ |
| 623 | #define ARM_SDEI_DP_EVENT_MAX_CNT 3 |
| 624 | |
| 625 | /* ARM SDEI dynamic shared event max count */ |
| 626 | #define ARM_SDEI_DS_EVENT_MAX_CNT 3 |
| 627 | #else |
Jeenu Viswambharan | a5acc0a | 2017-09-22 08:32:10 +0100 | [diff] [blame] | 628 | /* ARM SDEI dynamic private event numbers */ |
| 629 | #define ARM_SDEI_DP_EVENT_0 1000 |
| 630 | #define ARM_SDEI_DP_EVENT_1 1001 |
| 631 | #define ARM_SDEI_DP_EVENT_2 1002 |
| 632 | |
| 633 | /* ARM SDEI dynamic shared event numbers */ |
| 634 | #define ARM_SDEI_DS_EVENT_0 2000 |
| 635 | #define ARM_SDEI_DS_EVENT_1 2001 |
| 636 | #define ARM_SDEI_DS_EVENT_2 2002 |
| 637 | |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 638 | #define ARM_SDEI_PRIVATE_EVENTS \ |
| 639 | SDEI_DEFINE_EVENT_0(ARM_SDEI_SGI), \ |
| 640 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 641 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 642 | SDEI_PRIVATE_EVENT(ARM_SDEI_DP_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
| 643 | |
| 644 | #define ARM_SDEI_SHARED_EVENTS \ |
| 645 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_0, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 646 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_1, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC), \ |
| 647 | SDEI_SHARED_EVENT(ARM_SDEI_DS_EVENT_2, SDEI_DYN_IRQ, SDEI_MAPF_DYNAMIC) |
Balint Dobszay | d0dbd5e | 2019-12-18 15:28:00 +0100 | [diff] [blame] | 648 | #endif /* SDEI_IN_FCONF */ |
Jeenu Viswambharan | 6e28446 | 2017-12-08 10:38:24 +0000 | [diff] [blame] | 649 | |
Antonio Nino Diaz | 6f3ccc5 | 2018-07-20 09:17:26 +0100 | [diff] [blame] | 650 | #endif /* ARM_DEF_H */ |