Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. |
| 3 | * |
dp-arm | fa3cf0b | 2017-05-03 09:38:09 +0100 | [diff] [blame] | 4 | * SPDX-License-Identifier: BSD-3-Clause |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 5 | */ |
| 6 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 7 | #ifndef PMU_H |
| 8 | #define PMU_H |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 9 | |
Xing Zheng | b4bcc1d | 2017-02-24 16:26:11 +0800 | [diff] [blame] | 10 | #include <pmu_bits.h> |
Caesar Wang | 0620bb8 | 2016-10-27 01:10:28 +0800 | [diff] [blame] | 11 | #include <pmu_regs.h> |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 12 | #include <soc.h> |
Caesar Wang | 0620bb8 | 2016-10-27 01:10:28 +0800 | [diff] [blame] | 13 | |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 14 | /* Allocate sp reginon in pmusram */ |
| 15 | #define PSRAM_SP_SIZE 0x80 |
| 16 | #define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE) |
| 17 | |
| 18 | /***************************************************************************** |
| 19 | * Common define for per soc pmu.h |
| 20 | *****************************************************************************/ |
| 21 | /* The ways of cores power domain contorlling */ |
| 22 | enum cores_pm_ctr_mode { |
| 23 | core_pwr_pd = 0, |
| 24 | core_pwr_wfi = 1, |
| 25 | core_pwr_wfi_int = 2 |
| 26 | }; |
| 27 | |
| 28 | /***************************************************************************** |
| 29 | * pmu con,reg |
| 30 | *****************************************************************************/ |
| 31 | #define PMU_WKUP_CFG(n) ((n) * 4) |
| 32 | |
| 33 | #define PMU_CORE_PM_CON(cpu) (0xc0 + (cpu * 4)) |
| 34 | |
| 35 | /* the shift of bits for cores status */ |
| 36 | enum pmu_core_pwrst_shift { |
| 37 | clstl_cpu_wfe = 2, |
| 38 | clstl_cpu_wfi = 6, |
| 39 | clstb_cpu_wfe = 12, |
| 40 | clstb_cpu_wfi = 16 |
| 41 | }; |
| 42 | |
| 43 | #define CKECK_WFE_MSK 0x1 |
| 44 | #define CKECK_WFI_MSK 0x10 |
| 45 | #define CKECK_WFEI_MSK 0x11 |
| 46 | |
Caesar Wang | 0620bb8 | 2016-10-27 01:10:28 +0800 | [diff] [blame] | 47 | /* Specific features required */ |
Caesar Wang | 59e41b5 | 2016-04-10 14:11:07 +0800 | [diff] [blame] | 48 | #define AP_PWROFF 0x0a |
Caesar Wang | ad39cfe | 2016-07-21 10:36:22 +0800 | [diff] [blame] | 49 | |
Caesar Wang | 3e8548b | 2016-08-25 06:31:32 +0800 | [diff] [blame] | 50 | #define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0) |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 51 | #define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12) |
Caesar Wang | ad39cfe | 2016-07-21 10:36:22 +0800 | [diff] [blame] | 52 | |
Caesar Wang | d1b9d2d | 2016-05-25 19:05:19 +0800 | [diff] [blame] | 53 | #define TSADC_INT_PIN 38 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 54 | #define CORES_PM_DISABLE 0x0 |
| 55 | |
Derek Basehore | 4ab3a96 | 2018-01-23 15:44:31 -0800 | [diff] [blame] | 56 | #define PD_CTR_LOOP 10000 |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 57 | #define CHK_CPU_LOOP 500 |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 58 | #define MAX_WAIT_COUNT 1000 |
| 59 | |
| 60 | #define GRF_SOC_CON4 0x0e210 |
Caesar Wang | 5045a1c | 2016-09-10 02:47:53 +0800 | [diff] [blame] | 61 | |
Caesar Wang | 3e8548b | 2016-08-25 06:31:32 +0800 | [diff] [blame] | 62 | #define PMUGRF_GPIO0A_SMT 0x0120 |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 63 | #define PMUGRF_SOC_CON0 0x0180 |
| 64 | |
| 65 | #define CCI_FORCE_WAKEUP WMSK_BIT(8) |
| 66 | #define EXTERNAL_32K WMSK_BIT(0) |
| 67 | |
| 68 | #define PLL_PD_HW 0xff |
| 69 | #define IOMUX_CLK_32K 0x00030002 |
| 70 | #define NOC_AUTO_ENABLE 0x3fffffff |
| 71 | |
| 72 | #define SAVE_QOS(array, NAME) \ |
| 73 | RK3399_CPU_AXI_SAVE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) |
| 74 | #define RESTORE_QOS(array, NAME) \ |
| 75 | RK3399_CPU_AXI_RESTORE_QOS(array, CPU_AXI_##NAME##_QOS_BASE) |
| 76 | |
| 77 | #define RK3399_CPU_AXI_SAVE_QOS(array, base) do { \ |
| 78 | array[0] = mmio_read_32(base + CPU_AXI_QOS_ID_COREID); \ |
| 79 | array[1] = mmio_read_32(base + CPU_AXI_QOS_REVISIONID); \ |
| 80 | array[2] = mmio_read_32(base + CPU_AXI_QOS_PRIORITY); \ |
| 81 | array[3] = mmio_read_32(base + CPU_AXI_QOS_MODE); \ |
| 82 | array[4] = mmio_read_32(base + CPU_AXI_QOS_BANDWIDTH); \ |
| 83 | array[5] = mmio_read_32(base + CPU_AXI_QOS_SATURATION); \ |
| 84 | array[6] = mmio_read_32(base + CPU_AXI_QOS_EXTCONTROL); \ |
| 85 | } while (0) |
| 86 | |
| 87 | #define RK3399_CPU_AXI_RESTORE_QOS(array, base) do { \ |
| 88 | mmio_write_32(base + CPU_AXI_QOS_ID_COREID, array[0]); \ |
| 89 | mmio_write_32(base + CPU_AXI_QOS_REVISIONID, array[1]); \ |
| 90 | mmio_write_32(base + CPU_AXI_QOS_PRIORITY, array[2]); \ |
| 91 | mmio_write_32(base + CPU_AXI_QOS_MODE, array[3]); \ |
| 92 | mmio_write_32(base + CPU_AXI_QOS_BANDWIDTH, array[4]); \ |
| 93 | mmio_write_32(base + CPU_AXI_QOS_SATURATION, array[5]); \ |
| 94 | mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \ |
| 95 | } while (0) |
| 96 | |
| 97 | struct pmu_slpdata_s { |
| 98 | uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 99 | uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 100 | uint32_t dmac0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 101 | uint32_t dmac1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 102 | uint32_t dcf_qos[CPU_AXI_QOS_NUM_REGS]; |
| 103 | uint32_t crypto0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 104 | uint32_t crypto1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 105 | uint32_t pmu_cm0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 106 | uint32_t peri_cm1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 107 | uint32_t gic_qos[CPU_AXI_QOS_NUM_REGS]; |
| 108 | uint32_t sdmmc_qos[CPU_AXI_QOS_NUM_REGS]; |
| 109 | uint32_t gmac_qos[CPU_AXI_QOS_NUM_REGS]; |
| 110 | uint32_t emmc_qos[CPU_AXI_QOS_NUM_REGS]; |
| 111 | uint32_t usb_otg0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 112 | uint32_t usb_otg1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 113 | uint32_t usb_host0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 114 | uint32_t usb_host1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 115 | uint32_t gpu_qos[CPU_AXI_QOS_NUM_REGS]; |
| 116 | uint32_t video_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 117 | uint32_t video_m1_r_qos[CPU_AXI_QOS_NUM_REGS]; |
| 118 | uint32_t video_m1_w_qos[CPU_AXI_QOS_NUM_REGS]; |
| 119 | uint32_t rga_r_qos[CPU_AXI_QOS_NUM_REGS]; |
| 120 | uint32_t rga_w_qos[CPU_AXI_QOS_NUM_REGS]; |
| 121 | uint32_t vop_big_r[CPU_AXI_QOS_NUM_REGS]; |
| 122 | uint32_t vop_big_w[CPU_AXI_QOS_NUM_REGS]; |
| 123 | uint32_t vop_little[CPU_AXI_QOS_NUM_REGS]; |
| 124 | uint32_t iep_qos[CPU_AXI_QOS_NUM_REGS]; |
| 125 | uint32_t isp1_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 126 | uint32_t isp1_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 127 | uint32_t isp0_m0_qos[CPU_AXI_QOS_NUM_REGS]; |
| 128 | uint32_t isp0_m1_qos[CPU_AXI_QOS_NUM_REGS]; |
| 129 | uint32_t hdcp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 130 | uint32_t perihp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 131 | uint32_t perilp_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 132 | uint32_t perilpslv_nsp_qos[CPU_AXI_QOS_NUM_REGS]; |
| 133 | uint32_t sdio_qos[CPU_AXI_QOS_NUM_REGS]; |
| 134 | }; |
Tony Xie | f6118cc | 2016-01-15 17:17:32 +0800 | [diff] [blame] | 135 | |
Tony Xie | 42e113e | 2016-07-16 11:16:51 +0800 | [diff] [blame] | 136 | extern uint32_t clst_warmboot_data[PLATFORM_CLUSTER_COUNT]; |
Caesar Wang | 5339d18 | 2016-10-27 01:13:34 +0800 | [diff] [blame] | 137 | |
| 138 | extern void sram_func_set_ddrctl_pll(uint32_t pll_src); |
| 139 | |
Antonio Nino Diaz | 5eb8837 | 2018-11-08 10:20:19 +0000 | [diff] [blame^] | 140 | #endif /* PMU_H */ |