rockchip: fixes typo and some bugs for suspend/resume tests
1. Remove the AP_PWROFF in ATF, should configure it in kernel.
2. Save and restore the PWMs pin/regs for suspend/resume.
3. The pmusgrf reset-hold bits needs to be released. since the
pmusgrf reset-hold bits needs to be held.
4. Configure the PMU power up/down cycles about delay 3ms.
5. With the MMIO register block as one big mapping.
6. Fix the build error with psci_entrypoint since PSCI lib updated.
Fixes the commit
9ec78bd ("rockchip: support the suspend/resume for rk3399").
Change-Id: I112806700bf433c87763aac23d22fa7e6a7f5264
diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.h b/plat/rockchip/rk3399/drivers/pmu/pmu.h
index 797282f..ddb1c16 100644
--- a/plat/rockchip/rk3399/drivers/pmu/pmu.h
+++ b/plat/rockchip/rk3399/drivers/pmu/pmu.h
@@ -810,10 +810,20 @@
#define PMUGRF_GPIO0A_IOMUX 0x00
#define PMUGRF_GPIO1A_IOMUX 0x10
+#define PMUGRF_GPIO1C_IOMUX 0x18
+
#define AP_PWROFF 0x0a
+
#define GPIO0A6_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 12)
#define GPIO0A6_IOMUX_PWM BITS_WITH_WMASK(1, 3, 12)
+#define GPIO1C3_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 6)
+#define GPIO1C3_IOMUX_PWM BITS_WITH_WMASK(1, 3, 6)
+#define GPIO4C2_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 4)
+#define GPIO4C2_IOMUX_PWM BITS_WITH_WMASK(1, 3, 4)
+#define GPIO4C6_IOMUX_GPIO BITS_WITH_WMASK(0, 3, 12)
+#define GPIO4C6_IOMUX_PWM BITS_WITH_WMASK(1, 3, 12)
#define GPIO1A6_IOMUX BITS_WITH_WMASK(0, 3, 12)
+
#define TSADC_INT_PIN 38
#define CORES_PM_DISABLE 0x0
#define CPU_AXI_QOS_ID_COREID 0x00
@@ -867,6 +877,8 @@
#define MAX_WAIT_COUNT 1000
#define GRF_SOC_CON4 0x0e210
+#define GRF_GPIO4C_IOMUX 0x0e028
+
#define PMUGRF_SOC_CON0 0x0180
#define CCI_FORCE_WAKEUP WMSK_BIT(8)
@@ -901,6 +913,15 @@
mmio_write_32(base + CPU_AXI_QOS_EXTCONTROL, array[6]); \
} while (0)
+/* there are 4 PWMs on rk3399 */
+struct pwm_data_s {
+ uint32_t iomux_bitmask;
+ uint64_t cnt[4];
+ uint64_t duty[4];
+ uint64_t period[4];
+ uint64_t ctrl[4];
+};
+
struct pmu_slpdata_s {
uint32_t cci_m0_qos[CPU_AXI_QOS_NUM_REGS];
uint32_t cci_m1_qos[CPU_AXI_QOS_NUM_REGS];