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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
Michael Brandlafdff3c2018-02-22 16:30:30 +01002 * Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
Haojian Zhuang5f281b32017-05-24 08:45:05 +08003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +00007#ifndef HIKEY_DEF_H
8#define HIKEY_DEF_H
Haojian Zhuang5f281b32017-05-24 08:45:05 +08009
Haojian Zhuang5f281b32017-05-24 08:45:05 +080010/* Always assume DDR is 1GB size. */
11#define DDR_BASE 0x0
Victor Chonga66e4592017-07-12 16:27:51 +090012#define DDR_SIZE 0x40000000
Haojian Zhuang5f281b32017-05-24 08:45:05 +080013
14#define DEVICE_BASE 0xF4000000
15#define DEVICE_SIZE 0x05800000
16
Victor Chongb9a8db22017-05-28 00:14:25 +090017/* Memory location options for TSP */
18#define HIKEY_SRAM_ID 0
19#define HIKEY_DRAM_ID 1
20
21/*
22 * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
23 * regions
24 * - Secure DDR (default is the top 16MB) used by OP-TEE
25 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
26 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
27 * - Non-secure DDR (8MB) reserved for OP-TEE's future use
28 */
29#define DDR_SEC_SIZE 0x01000000
Victor Chong7d787f52017-08-16 13:53:56 +090030#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE) /* 0x3F000000 */
Victor Chongb9a8db22017-05-28 00:14:25 +090031
32#define DDR_SDP_SIZE 0x00400000
33#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
34 DDR_SDP_SIZE)
35
Haojian Zhuang5f281b32017-05-24 08:45:05 +080036#define SRAM_BASE 0xFFF80000
37#define SRAM_SIZE 0x00012000
38
39/*
Haojian Zhuang5f281b32017-05-24 08:45:05 +080040 * PL011 related constants
41 */
42#define PL011_UART0_BASE 0xF8015000
43#define PL011_UART3_BASE 0xF7113000
44#define PL011_BAUDRATE 115200
45#define PL011_UART_CLK_IN_HZ 19200000
46
47#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
48#define HIKEY_USB_DESC_SIZE 0x00100000
49#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
50#define HIKEY_USB_DATA_SIZE 0x10000000
51#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
52#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
53#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
54 HIKEY_FB_BUFFER_SIZE)
55#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
56
57#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
58#define HIKEY_USB_DESC_IN_SIZE 0x00040000
59#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
60 HIKEY_USB_DESC_IN_SIZE)
61#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
62#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
63 HIKEY_USB_DESC_EP0_OUT_SIZE)
64#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
65
66#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
67#define HIKEY_MMC_DESC_SIZE 0x00100000
68
69/*
70 * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
71 * and eMMC driver. Since it could avoid to memory copy.
72 * So this SRAM region is used twice. First, it's used in BL1 as temporary
73 * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
74 * needs to be clear before used in BL2.
75 */
76#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
77#define HIKEY_MMC_DATA_SIZE 0x20000000
78#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
79#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
80#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
81#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
82 HIKEY_BL1_MMC_DESC_SIZE)
83#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
84
85#define EMMC_BASE 0
86#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20))
87#define HIKEY_FIP_MAX_SIZE (8 << 20)
88#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
89#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
90#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
91#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
92
93/*
94 * GIC400 interrupt handling related constants
95 */
96#define IRQ_SEC_PHY_TIMER 29
97#define IRQ_SEC_SGI_0 8
98#define IRQ_SEC_SGI_1 9
99#define IRQ_SEC_SGI_2 10
100#define IRQ_SEC_SGI_3 11
101#define IRQ_SEC_SGI_4 12
102#define IRQ_SEC_SGI_5 13
103#define IRQ_SEC_SGI_6 14
104#define IRQ_SEC_SGI_7 15
105#define IRQ_SEC_SGI_8 16
106
Antonio Nino Diaz5eb88372018-11-08 10:20:19 +0000107#endif /* HIKEY_DEF_H */