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Haojian Zhuang5f281b32017-05-24 08:45:05 +08001/*
2 * Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef __HIKEY_DEF_H__
8#define __HIKEY_DEF_H__
9
10#include <common_def.h>
11#include <tbbr_img_def.h>
12
13/* Always assume DDR is 1GB size. */
14#define DDR_BASE 0x0
Victor Chonga66e4592017-07-12 16:27:51 +090015#define DDR_SIZE 0x40000000
Haojian Zhuang5f281b32017-05-24 08:45:05 +080016
17#define DEVICE_BASE 0xF4000000
18#define DEVICE_SIZE 0x05800000
19
20#define XG2RAM0_BASE 0xF9800000
21#define XG2RAM0_SIZE 0x00400000
22
Victor Chongb9a8db22017-05-28 00:14:25 +090023/* Memory location options for TSP */
24#define HIKEY_SRAM_ID 0
25#define HIKEY_DRAM_ID 1
26
27/*
28 * DDR for OP-TEE (32MB from 0x3E00000-0x3FFFFFFF) is divided in several
29 * regions
30 * - Secure DDR (default is the top 16MB) used by OP-TEE
31 * - Non-secure DDR used by OP-TEE (shared memory and padding) (4MB)
32 * - Secure DDR (4MB aligned on 4MB) for OP-TEE's "Secure Data Path" feature
33 * - Non-secure DDR (8MB) reserved for OP-TEE's future use
34 */
35#define DDR_SEC_SIZE 0x01000000
36#define DDR_SEC_BASE (DDR_BASE + DDR_SIZE - DDR_SEC_SIZE)
37
38#define DDR_SDP_SIZE 0x00400000
39#define DDR_SDP_BASE (DDR_SEC_BASE - 0x400000 /* align */ - \
40 DDR_SDP_SIZE)
41
Haojian Zhuang5f281b32017-05-24 08:45:05 +080042#define SRAM_BASE 0xFFF80000
43#define SRAM_SIZE 0x00012000
44
45/*
46 * BL1 is stored in XG2RAM0_HIRQ that is 784KB large (0xF980_0000~0xF98C_4000).
47 */
48#define ONCHIPROM_PARAM_BASE (XG2RAM0_BASE + 0x700)
49#define LOADER_RAM_BASE (XG2RAM0_BASE + 0x800)
50#define BL1_XG2RAM0_OFFSET 0x1000
51
52/*
53 * PL011 related constants
54 */
55#define PL011_UART0_BASE 0xF8015000
56#define PL011_UART3_BASE 0xF7113000
57#define PL011_BAUDRATE 115200
58#define PL011_UART_CLK_IN_HZ 19200000
59
60#define HIKEY_USB_DESC_BASE (DDR_BASE + 0x00800000)
61#define HIKEY_USB_DESC_SIZE 0x00100000
62#define HIKEY_USB_DATA_BASE (DDR_BASE + 0x10000000)
63#define HIKEY_USB_DATA_SIZE 0x10000000
64#define HIKEY_FB_BUFFER_BASE (HIKEY_USB_DATA_BASE)
65#define HIKEY_FB_BUFFER_SIZE HIKEY_USB_DATA_SIZE
66#define HIKEY_FB_DOWNLOAD_BASE (HIKEY_FB_BUFFER_BASE + \
67 HIKEY_FB_BUFFER_SIZE)
68#define HIKEY_FB_DOWNLOAD_SIZE HIKEY_USB_DATA_SIZE
69
70#define HIKEY_USB_DESC_IN_BASE (DDR_BASE + 0x00800000)
71#define HIKEY_USB_DESC_IN_SIZE 0x00040000
72#define HIKEY_USB_DESC_EP0_OUT_BASE (HIKEY_USB_DESC_IN_BASE + \
73 HIKEY_USB_DESC_IN_SIZE)
74#define HIKEY_USB_DESC_EP0_OUT_SIZE 0x00040000
75#define HIKEY_USB_DESC_EPX_OUT_BASE (HIKEY_USB_DESC_EP0_OUT_BASE + \
76 HIKEY_USB_DESC_EP0_OUT_SIZE)
77#define HIKEY_USB_DESC_EPX_OUT_SIZE 0x00080000
78
79#define HIKEY_MMC_DESC_BASE (DDR_BASE + 0x03000000)
80#define HIKEY_MMC_DESC_SIZE 0x00100000
81
82/*
83 * HIKEY_MMC_DATA_BASE & HIKEY_MMC_DATA_SIZE are shared between fastboot
84 * and eMMC driver. Since it could avoid to memory copy.
85 * So this SRAM region is used twice. First, it's used in BL1 as temporary
86 * buffer in eMMC driver. Second, it's used by MCU in BL2. The SRAM region
87 * needs to be clear before used in BL2.
88 */
89#define HIKEY_MMC_DATA_BASE (DDR_BASE + 0x10000000)
90#define HIKEY_MMC_DATA_SIZE 0x20000000
91#define HIKEY_NS_IMAGE_OFFSET (DDR_BASE + 0x35000000)
92#define HIKEY_BL1_MMC_DESC_BASE (SRAM_BASE)
93#define HIKEY_BL1_MMC_DESC_SIZE 0x00001000
94#define HIKEY_BL1_MMC_DATA_BASE (HIKEY_BL1_MMC_DESC_BASE + \
95 HIKEY_BL1_MMC_DESC_SIZE)
96#define HIKEY_BL1_MMC_DATA_SIZE 0x0000B000
97
98#define EMMC_BASE 0
99#define HIKEY_FIP_BASE (EMMC_BASE + (4 << 20))
100#define HIKEY_FIP_MAX_SIZE (8 << 20)
101#define HIKEY_EMMC_RPMB_BASE (EMMC_BASE + 0)
102#define HIKEY_EMMC_RPMB_MAX_SIZE (128 << 10)
103#define HIKEY_EMMC_USERDATA_BASE (EMMC_BASE + 0)
104#define HIKEY_EMMC_USERDATA_MAX_SIZE (4 << 30)
105
106/*
107 * GIC400 interrupt handling related constants
108 */
109#define IRQ_SEC_PHY_TIMER 29
110#define IRQ_SEC_SGI_0 8
111#define IRQ_SEC_SGI_1 9
112#define IRQ_SEC_SGI_2 10
113#define IRQ_SEC_SGI_3 11
114#define IRQ_SEC_SGI_4 12
115#define IRQ_SEC_SGI_5 13
116#define IRQ_SEC_SGI_6 14
117#define IRQ_SEC_SGI_7 15
118#define IRQ_SEC_SGI_8 16
119
120#endif /* __HIKEY_DEF_H__ */