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Dan Handley9df48042015-03-19 18:58:55 +00001/*
Alexei Fedorov896799a2019-05-09 12:14:40 +01002 * Copyright (c) 2015-2019, ARM Limited and Contributors. All rights reserved.
Dan Handley9df48042015-03-19 18:58:55 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Dan Handley9df48042015-03-19 18:58:55 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8
9#include <platform_def.h>
10
Dan Handley9df48042015-03-19 18:58:55 +000011#include <arch.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000012#include <bl1/bl1.h>
13#include <common/bl_common.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils.h>
15#include <lib/xlat_tables/xlat_tables_compat.h>
Antonio Nino Diazbd7b7402019-01-25 14:30:04 +000016#include <plat/arm/common/plat_arm.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000017#include <plat/common/platform.h>
18
Dan Handley9df48042015-03-19 18:58:55 +000019/* Weak definitions may be overridden in specific ARM standard platform */
20#pragma weak bl1_early_platform_setup
21#pragma weak bl1_plat_arch_setup
Dan Handley9df48042015-03-19 18:58:55 +000022#pragma weak bl1_plat_sec_mem_layout
Yatharth Kocharede39cb2016-11-14 12:01:04 +000023#pragma weak bl1_plat_prepare_exit
Sathees Balya22576072018-09-03 17:41:13 +010024#pragma weak bl1_plat_get_next_image_id
25#pragma weak plat_arm_bl1_fwu_needed
Dan Handley9df48042015-03-19 18:58:55 +000026
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010027#define MAP_BL1_TOTAL MAP_REGION_FLAT( \
28 bl1_tzram_layout.total_base, \
29 bl1_tzram_layout.total_size, \
30 MT_MEMORY | MT_RW | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010031/*
32 * If SEPARATE_CODE_AND_RODATA=1 we define a region for each section
33 * otherwise one region is defined containing both
34 */
35#if SEPARATE_CODE_AND_RODATA
36#define MAP_BL1_RO MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010037 BL_CODE_BASE, \
38 BL1_CODE_END - BL_CODE_BASE, \
Daniel Boulby4e97abd2018-07-16 14:09:15 +010039 MT_CODE | MT_SECURE), \
40 MAP_REGION_FLAT( \
Daniel Boulby45a2c9e2018-07-06 16:54:44 +010041 BL1_RO_DATA_BASE, \
42 BL1_RO_DATA_END \
43 - BL_RO_DATA_BASE, \
44 MT_RO_DATA | MT_SECURE)
Daniel Boulby4e97abd2018-07-16 14:09:15 +010045#else
46#define MAP_BL1_RO MAP_REGION_FLAT( \
47 BL_CODE_BASE, \
48 BL1_CODE_END - BL_CODE_BASE, \
49 MT_CODE | MT_SECURE)
50#endif
Dan Handley9df48042015-03-19 18:58:55 +000051
52/* Data structure which holds the extents of the trusted SRAM for BL1*/
53static meminfo_t bl1_tzram_layout;
54
Sandrine Bailleuxb3b6e222018-07-11 12:44:22 +020055struct meminfo *bl1_plat_sec_mem_layout(void)
Dan Handley9df48042015-03-19 18:58:55 +000056{
57 return &bl1_tzram_layout;
58}
59
60/*******************************************************************************
61 * BL1 specific platform actions shared between ARM standard platforms.
62 ******************************************************************************/
63void arm_bl1_early_platform_setup(void)
64{
Dan Handley9df48042015-03-19 18:58:55 +000065
Juan Castillob6132f12015-10-06 14:01:35 +010066#if !ARM_DISABLE_TRUSTED_WDOG
67 /* Enable watchdog */
Aditya Angadi20b48412019-04-16 11:29:14 +053068 plat_arm_secure_wdt_start();
Juan Castillob6132f12015-10-06 14:01:35 +010069#endif
70
Dan Handley9df48042015-03-19 18:58:55 +000071 /* Initialize the console to provide early debug support */
Antonio Nino Diaz23ede6a2018-06-19 09:29:36 +010072 arm_console_boot_init();
Dan Handley9df48042015-03-19 18:58:55 +000073
74 /* Allow BL1 to see the whole Trusted RAM */
75 bl1_tzram_layout.total_base = ARM_BL_RAM_BASE;
76 bl1_tzram_layout.total_size = ARM_BL_RAM_SIZE;
Dan Handley9df48042015-03-19 18:58:55 +000077}
78
79void bl1_early_platform_setup(void)
80{
81 arm_bl1_early_platform_setup();
82
83 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000084 * Initialize Interconnect for this cluster during cold boot.
Dan Handley9df48042015-03-19 18:58:55 +000085 * No need for locks as no other CPU is active.
86 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000087 plat_arm_interconnect_init();
Dan Handley9df48042015-03-19 18:58:55 +000088 /*
Vikram Kanigirifbb13012016-02-15 11:54:14 +000089 * Enable Interconnect coherency for the primary CPU's cluster.
Dan Handley9df48042015-03-19 18:58:55 +000090 */
Vikram Kanigirifbb13012016-02-15 11:54:14 +000091 plat_arm_interconnect_enter_coherency();
Dan Handley9df48042015-03-19 18:58:55 +000092}
93
94/******************************************************************************
95 * Perform the very early platform specific architecture setup shared between
96 * ARM standard platforms. This only does basic initialization. Later
97 * architectural setup (bl1_arch_setup()) does not do anything platform
98 * specific.
99 *****************************************************************************/
100void arm_bl1_plat_arch_setup(void)
101{
Soby Mathewb9856482018-09-18 11:42:42 +0100102#if USE_COHERENT_MEM && !ARM_CRYPTOCELL_INTEG
103 /*
104 * Ensure ARM platforms don't use coherent memory in BL1 unless
105 * cryptocell integration is enabled.
106 */
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100107 assert((BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE) == 0U);
Dan Handley9df48042015-03-19 18:58:55 +0000108#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100109
110 const mmap_region_t bl_regions[] = {
111 MAP_BL1_TOTAL,
Daniel Boulby4e97abd2018-07-16 14:09:15 +0100112 MAP_BL1_RO,
Roberto Vargase3adc372018-05-23 09:27:06 +0100113#if USE_ROMLIB
114 ARM_MAP_ROMLIB_CODE,
115 ARM_MAP_ROMLIB_DATA,
Soby Mathewb9856482018-09-18 11:42:42 +0100116#endif
117#if ARM_CRYPTOCELL_INTEG
118 ARM_MAP_BL_COHERENT_RAM,
119#endif
Daniel Boulby45a2c9e2018-07-06 16:54:44 +0100120 {0}
121 };
122
Roberto Vargas344ff022018-10-19 16:44:18 +0100123 setup_page_tables(bl_regions, plat_arm_get_mmap());
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100124#ifdef AARCH32
Antonio Nino Diaz533d3a82018-08-07 16:35:19 +0100125 enable_mmu_svc_mon(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100126#else
Sandrine Bailleux4a1267a2016-05-18 16:11:47 +0100127 enable_mmu_el3(0);
Yatharth Kochar88ac53b2016-07-04 11:03:49 +0100128#endif /* AARCH32 */
Roberto Vargase3adc372018-05-23 09:27:06 +0100129
130 arm_setup_romlib();
Dan Handley9df48042015-03-19 18:58:55 +0000131}
132
133void bl1_plat_arch_setup(void)
134{
135 arm_bl1_plat_arch_setup();
136}
137
138/*
139 * Perform the platform specific architecture setup shared between
140 * ARM standard platforms.
141 */
142void arm_bl1_platform_setup(void)
143{
144 /* Initialise the IO layer and register platform IO devices */
145 plat_arm_io_setup();
Soby Mathew7c6df5b2018-01-15 14:43:42 +0000146 arm_load_tb_fw_config();
John Tsichritzisc34341a2018-07-30 13:41:52 +0100147#if TRUSTED_BOARD_BOOT
148 /* Share the Mbed TLS heap info with other images */
149 arm_bl1_set_mbedtls_heap();
150#endif /* TRUSTED_BOARD_BOOT */
Antonio Nino Diaz05f49572018-09-25 11:37:23 +0100151
Soby Mathewd969a7e2018-06-11 16:40:36 +0100152 /*
153 * Allow access to the System counter timer module and program
154 * counter frequency for non secure images during FWU
155 */
Usama Arife97998f2018-11-30 15:43:56 +0000156#ifdef ARM_SYS_TIMCTL_BASE
Soby Mathewd969a7e2018-06-11 16:40:36 +0100157 arm_configure_sys_timer();
Usama Arife97998f2018-11-30 15:43:56 +0000158#endif
Usama Arif078e66f2018-12-12 17:14:29 +0000159#if (ARM_ARCH_MAJOR > 7) || defined(ARMV7_SUPPORTS_GENERIC_TIMER)
Soby Mathewd969a7e2018-06-11 16:40:36 +0100160 write_cntfrq_el0(plat_get_syscnt_freq2());
Usama Arif078e66f2018-12-12 17:14:29 +0000161#endif
Dan Handley9df48042015-03-19 18:58:55 +0000162}
163
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000164void bl1_plat_prepare_exit(entry_point_info_t *ep_info)
165{
Juan Castillob6132f12015-10-06 14:01:35 +0100166#if !ARM_DISABLE_TRUSTED_WDOG
167 /* Disable watchdog before leaving BL1 */
Aditya Angadi20b48412019-04-16 11:29:14 +0530168 plat_arm_secure_wdt_stop();
Juan Castillob6132f12015-10-06 14:01:35 +0100169#endif
170
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000171#ifdef EL3_PAYLOAD_BASE
172 /*
173 * Program the EL3 payload's entry point address into the CPUs mailbox
174 * in order to release secondary CPUs from their holding pen and make
175 * them jump there.
176 */
Dimitris Papastamosd7a36512018-06-18 13:01:06 +0100177 plat_arm_program_trusted_mailbox(ep_info->pc);
Sandrine Bailleux03897bb2015-11-26 16:31:34 +0000178 dsbsy();
179 sev();
180#endif
181}
Soby Mathew94273572018-03-07 11:32:04 +0000182
Sathees Balya22576072018-09-03 17:41:13 +0100183/*
184 * On Arm platforms, the FWU process is triggered when the FIP image has
185 * been tampered with.
186 */
187int plat_arm_bl1_fwu_needed(void)
188{
189 return (arm_io_is_toc_valid() != 1);
190}
191
Soby Mathew94273572018-03-07 11:32:04 +0000192/*******************************************************************************
193 * The following function checks if Firmware update is needed,
194 * by checking if TOC in FIP image is valid or not.
195 ******************************************************************************/
196unsigned int bl1_plat_get_next_image_id(void)
197{
Sathees Balya22576072018-09-03 17:41:13 +0100198 if (plat_arm_bl1_fwu_needed() != 0)
Soby Mathew94273572018-03-07 11:32:04 +0000199 return NS_BL1U_IMAGE_ID;
200
201 return BL2_IMAGE_ID;
202}