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Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +00001/*
Bipin Ravicaa2e052022-02-23 23:45:50 -06002 * Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +00003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <common/debug.h>
8#include <common/runtime_svc.h>
Boyan Karatotev5d38cb32023-01-27 09:37:07 +00009#include <lib/cpus/errata.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <lib/cpus/wa_cve_2017_5715.h>
11#include <lib/cpus/wa_cve_2018_3639.h>
Bipin Ravicaa2e052022-02-23 23:45:50 -060012#include <lib/cpus/wa_cve_2022_23960.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000013#include <lib/smccc.h>
14#include <services/arm_arch_svc.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000015#include <smccc_helpers.h>
Manish V Badarkhef809c6e2020-02-22 08:43:00 +000016#include <plat/common/platform.h>
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +000017
18static int32_t smccc_version(void)
19{
20 return MAKE_SMCCC_VERSION(SMCCC_MAJOR_VERSION, SMCCC_MINOR_VERSION);
21}
22
Manish V Badarkhe709bc372020-04-28 13:25:56 +010023static int32_t smccc_arch_features(u_register_t arg1)
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +000024{
Manish V Badarkhef809c6e2020-02-22 08:43:00 +000025 switch (arg1) {
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +000026 case SMCCC_VERSION:
27 case SMCCC_ARCH_FEATURES:
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +010028 return SMC_ARCH_CALL_SUCCESS;
Manish V Badarkhef809c6e2020-02-22 08:43:00 +000029 case SMCCC_ARCH_SOC_ID:
Manish V Badarkhe80f13ee2020-07-23 20:23:01 +010030 return plat_is_smccc_feature_available(arg1);
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010031#if WORKAROUND_CVE_2017_5715
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +000032 case SMCCC_ARCH_WORKAROUND_1:
Dimitris Papastamos570c06a2018-04-06 15:29:34 +010033 if (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)
Dimitris Papastamos914757c2018-03-12 14:47:09 +000034 return 1;
Dimitris Papastamos6d1f4992018-03-28 12:06:40 +010035 return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
36#endif
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000037
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010038#if WORKAROUND_CVE_2018_3639
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000039 case SMCCC_ARCH_WORKAROUND_2: {
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010040#if DYNAMIC_WORKAROUND_CVE_2018_3639
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000041 unsigned long long ssbs;
42
43 /*
44 * Firmware doesn't have to carry out dynamic workaround if the
45 * PE implements architectural Speculation Store Bypass Safe
46 * (SSBS) feature.
47 */
Dimitris Papastamosb091eb92019-02-27 11:46:48 +000048 ssbs = (read_id_aa64pfr1_el1() >> ID_AA64PFR1_EL1_SSBS_SHIFT) &
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000049 ID_AA64PFR1_EL1_SSBS_MASK;
50
51 /*
52 * If architectural SSBS is available on this PE, no firmware
53 * mitigation via SMCCC_ARCH_WORKAROUND_2 is required.
54 */
55 if (ssbs != SSBS_UNAVAILABLE)
56 return 1;
57
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010058 /*
59 * On a platform where at least one CPU requires
60 * dynamic mitigation but others are either unaffected
61 * or permanently mitigated, report the latter as not
62 * needing dynamic mitigation.
63 */
64 if (wa_cve_2018_3639_get_disable_ptr() == NULL)
65 return 1;
66 /*
67 * If we get here, this CPU requires dynamic mitigation
68 * so report it as such.
69 */
70 return 0;
71#else
72 /* Either the CPUs are unaffected or permanently mitigated */
Manish V Badarkhe13335172020-02-19 13:36:50 +000073 return SMC_ARCH_CALL_NOT_REQUIRED;
Dimitris Papastamose6625ec2018-04-05 14:38:26 +010074#endif
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000075 }
Dimitris Papastamosba51d9e2018-05-16 11:36:14 +010076#endif
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000077
Bipin Ravicaa2e052022-02-23 23:45:50 -060078#if (WORKAROUND_CVE_2022_23960 || WORKAROUND_CVE_2017_5715)
79 case SMCCC_ARCH_WORKAROUND_3:
80 /*
81 * SMCCC_ARCH_WORKAROUND_3 should also take into account
82 * CVE-2017-5715 since this SMC can be used instead of
83 * SMCCC_ARCH_WORKAROUND_1.
84 */
85 if ((check_smccc_arch_wa3_applies() == ERRATA_NOT_APPLIES) &&
86 (check_wa_cve_2017_5715() == ERRATA_NOT_APPLIES)) {
87 return 1;
88 }
89 return 0; /* ERRATA_APPLIES || ERRATA_MISSING */
90#endif
91
Jeenu Viswambharanaa00aff2018-11-15 11:38:03 +000092 /* Fallthrough */
93
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +000094 default:
95 return SMC_UNK;
96 }
Manish V Badarkhe709bc372020-04-28 13:25:56 +010097}
98
99/* return soc revision or soc version on success otherwise
100 * return invalid parameter */
101static int32_t smccc_arch_id(u_register_t arg1)
102{
103 if (arg1 == SMCCC_GET_SOC_REVISION) {
104 return plat_get_soc_revision();
105 }
106 if (arg1 == SMCCC_GET_SOC_VERSION) {
107 return plat_get_soc_version();
108 }
109 return SMC_ARCH_CALL_INVAL_PARAM;
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000110}
111
112/*
113 * Top-level Arm Architectural Service SMC handler.
114 */
Roberto Vargas05712702018-02-12 12:36:17 +0000115static uintptr_t arm_arch_svc_smc_handler(uint32_t smc_fid,
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000116 u_register_t x1,
117 u_register_t x2,
118 u_register_t x3,
119 u_register_t x4,
120 void *cookie,
121 void *handle,
122 u_register_t flags)
123{
124 switch (smc_fid) {
125 case SMCCC_VERSION:
126 SMC_RET1(handle, smccc_version());
127 case SMCCC_ARCH_FEATURES:
Manish V Badarkhe709bc372020-04-28 13:25:56 +0100128 SMC_RET1(handle, smccc_arch_features(x1));
129 case SMCCC_ARCH_SOC_ID:
130 SMC_RET1(handle, smccc_arch_id(x1));
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000131#if WORKAROUND_CVE_2017_5715
132 case SMCCC_ARCH_WORKAROUND_1:
133 /*
134 * The workaround has already been applied on affected PEs
Bipin Ravicaa2e052022-02-23 23:45:50 -0600135 * during entry to EL3. On unaffected PEs, this function
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000136 * has no effect.
137 */
138 SMC_RET0(handle);
139#endif
Dimitris Papastamose6625ec2018-04-05 14:38:26 +0100140#if WORKAROUND_CVE_2018_3639
141 case SMCCC_ARCH_WORKAROUND_2:
142 /*
143 * The workaround has already been applied on affected PEs
144 * requiring dynamic mitigation during entry to EL3.
145 * On unaffected or statically mitigated PEs, this function
146 * has no effect.
147 */
148 SMC_RET0(handle);
149#endif
Bipin Ravicaa2e052022-02-23 23:45:50 -0600150#if (WORKAROUND_CVE_2022_23960 || WORKAROUND_CVE_2017_5715)
151 case SMCCC_ARCH_WORKAROUND_3:
152 /*
153 * The workaround has already been applied on affected PEs
154 * during entry to EL3. On unaffected PEs, this function
155 * has no effect.
156 */
157 SMC_RET0(handle);
158#endif
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000159 default:
160 WARN("Unimplemented Arm Architecture Service Call: 0x%x \n",
161 smc_fid);
162 SMC_RET1(handle, SMC_UNK);
163 }
164}
165
166/* Register Standard Service Calls as runtime service */
167DECLARE_RT_SVC(
168 arm_arch_svc,
169 OEN_ARM_START,
170 OEN_ARM_END,
171 SMC_TYPE_FAST,
172 NULL,
Dimitris Papastamos0dcdb1a2018-01-19 16:58:29 +0000173 arm_arch_svc_smc_handler
174);