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Manish V Badarkhef356f7e2021-06-29 11:44:20 +01001/*
Boyan Karatotev6468d4a2023-02-16 15:12:45 +00002 * Copyright (c) 2021-2023, Arm Limited. All rights reserved.
Manish V Badarkhef356f7e2021-06-29 11:44:20 +01003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#include <stdbool.h>
8
9#include <arch.h>
10#include <arch_helpers.h>
11#include <lib/extensions/sys_reg_trace.h>
12
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010013void sys_reg_trace_enable_per_world(per_world_context_t *per_world_ctx)
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010014{
Boyan Karatotev919d3c82023-02-13 16:32:47 +000015 /*
16 * CPTR_EL3.TTA: Set to zero so that System register accesses to the
17 * trace registers do not trap to EL3.
18 */
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010019 uint64_t val = per_world_ctx->ctx_cptr_el3;
Boyan Karatotev919d3c82023-02-13 16:32:47 +000020 val &= ~(TTA_BIT);
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010021 per_world_ctx->ctx_cptr_el3 = val;
Boyan Karatotev919d3c82023-02-13 16:32:47 +000022}
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010023
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010024void sys_reg_trace_disable_per_world(per_world_context_t *per_world_ctx)
Boyan Karatotev919d3c82023-02-13 16:32:47 +000025{
26 /*
27 * CPTR_EL3.TTA: Set to one so that System register accesses to the
28 * trace registers trap to EL3, unless it is trapped by CPACR.TRCDIS,
29 * CPACR_EL1.TTA, or CPTR_EL2.TTA
Andre Przywara44e33e02022-11-17 16:42:09 +000030 */
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010031 uint64_t val = per_world_ctx->ctx_cptr_el3;
Boyan Karatotev919d3c82023-02-13 16:32:47 +000032 val |= TTA_BIT;
Elizabeth Ho4fc00d22023-07-18 14:10:25 +010033 per_world_ctx->ctx_cptr_el3 = val;
Manish V Badarkhef356f7e2021-06-29 11:44:20 +010034}
Boyan Karatotev6468d4a2023-02-16 15:12:45 +000035
36void sys_reg_trace_init_el2_unused(void)
37{
38 /*
39 * CPTR_EL2.TTA: Set to zero so that Non-secure System register accesses
40 * to the trace registers from both Execution states do not trap to
41 * EL2. If PE trace unit System registers are not implemented then this
42 * bit is reserved, and must be set to zero.
43 */
44 write_cptr_el2(read_cptr_el2() & ~CPTR_EL2_TTA_BIT);
45}