Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2015 - 2020, Broadcom |
| 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | */ |
| 6 | |
| 7 | #ifndef CMN_PLAT_DEF_H |
| 8 | #define CMN_PLAT_DEF_H |
| 9 | |
Sheetal Tigadoli | ad0943e | 2019-12-18 19:44:43 +0530 | [diff] [blame] | 10 | #include <bcm_elog.h> |
| 11 | |
| 12 | #ifndef GET_LOG_LEVEL |
| 13 | #define GET_LOG_LEVEL() LOG_LEVEL |
| 14 | #endif |
| 15 | |
| 16 | #ifndef SET_LOG_LEVEL |
| 17 | #define SET_LOG_LEVEL(x) ((void)(x)) |
| 18 | #endif |
| 19 | |
| 20 | #define PLAT_LOG_NOTICE(...) \ |
| 21 | do { \ |
| 22 | if (GET_LOG_LEVEL() >= LOG_LEVEL_NOTICE) { \ |
| 23 | bcm_elog(LOG_MARKER_NOTICE __VA_ARGS__); \ |
| 24 | tf_log(LOG_MARKER_NOTICE __VA_ARGS__); \ |
| 25 | } \ |
| 26 | } while (0) |
| 27 | |
| 28 | #define PLAT_LOG_ERROR(...) \ |
| 29 | do { \ |
| 30 | if (GET_LOG_LEVEL() >= LOG_LEVEL_ERROR) { \ |
| 31 | bcm_elog(LOG_MARKER_ERROR, __VA_ARGS__); \ |
| 32 | tf_log(LOG_MARKER_ERROR __VA_ARGS__); \ |
| 33 | } \ |
| 34 | } while (0) |
| 35 | |
| 36 | #define PLAT_LOG_WARN(...) \ |
| 37 | do { \ |
| 38 | if (GET_LOG_LEVEL() >= LOG_LEVEL_WARNING) { \ |
| 39 | bcm_elog(LOG_MARKER_WARNING, __VA_ARGS__);\ |
| 40 | tf_log(LOG_MARKER_WARNING __VA_ARGS__); \ |
| 41 | } \ |
| 42 | } while (0) |
| 43 | |
| 44 | #define PLAT_LOG_INFO(...) \ |
| 45 | do { \ |
| 46 | if (GET_LOG_LEVEL() >= LOG_LEVEL_INFO) { \ |
| 47 | bcm_elog(LOG_MARKER_INFO __VA_ARGS__); \ |
| 48 | tf_log(LOG_MARKER_INFO __VA_ARGS__); \ |
| 49 | } \ |
| 50 | } while (0) |
| 51 | |
| 52 | #define PLAT_LOG_VERBOSE(...) \ |
| 53 | do { \ |
| 54 | if (GET_LOG_LEVEL() >= LOG_LEVEL_VERBOSE) { \ |
| 55 | bcm_elog(LOG_MARKER_VERBOSE __VA_ARGS__);\ |
| 56 | tf_log(LOG_MARKER_VERBOSE __VA_ARGS__); \ |
| 57 | } \ |
| 58 | } while (0) |
| 59 | |
Sheetal Tigadoli | 13680c9 | 2019-12-13 10:39:06 +0530 | [diff] [blame] | 60 | /* Print file and line number on assert */ |
| 61 | #define PLAT_LOG_LEVEL_ASSERT LOG_LEVEL_INFO |
| 62 | |
| 63 | /* |
| 64 | * The number of regions like RO(code), coherent and data required by |
| 65 | * different BL stages which need to be mapped in the MMU. |
| 66 | */ |
| 67 | #if USE_COHERENT_MEM |
| 68 | #define CMN_BL_REGIONS 3 |
| 69 | #else |
| 70 | #define CMN_BL_REGIONS 2 |
| 71 | #endif |
| 72 | |
| 73 | /* |
| 74 | * FIP definitions |
| 75 | */ |
| 76 | #define PLAT_FIP_ATTEMPT_OFFSET 0x20000 |
| 77 | #define PLAT_FIP_NUM_ATTEMPTS 128 |
| 78 | |
| 79 | #define PLAT_BRCM_FIP_QSPI_BASE QSPI_BASE_ADDR |
| 80 | #define PLAT_BRCM_FIP_NAND_BASE NAND_BASE_ADDR |
| 81 | #define PLAT_BRCM_FIP_MAX_SIZE 0x01000000 |
| 82 | |
| 83 | #define PLAT_BRCM_FIP_BASE PLAT_BRCM_FIP_QSPI_BASE |
| 84 | #endif |