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Achin Gupta7aea9082014-02-01 07:51:28 +00001/*
Paul Beesley1fbc97b2019-01-11 18:26:51 +00002 * Copyright (c) 2013-2019, ARM Limited and Contributors. All rights reserved.
Achin Gupta7aea9082014-02-01 07:51:28 +00003 *
dp-armfa3cf0b2017-05-03 09:38:09 +01004 * SPDX-License-Identifier: BSD-3-Clause
Achin Gupta7aea9082014-02-01 07:51:28 +00005 */
6
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00007#include <assert.h>
8#include <stdbool.h>
9#include <string.h>
10
11#include <platform_def.h>
12
Achin Gupta27b895e2014-05-04 18:38:28 +010013#include <arch.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000014#include <arch_helpers.h>
Soby Mathew830f0ad2019-07-12 09:23:38 +010015#include <arch_features.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000016#include <bl31/interrupt_mgmt.h>
17#include <common/bl_common.h>
Dan Handley2bd4ef22014-04-09 13:14:54 +010018#include <context.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000019#include <lib/el3_runtime/context_mgmt.h>
20#include <lib/el3_runtime/pubsub_events.h>
21#include <lib/extensions/amu.h>
22#include <lib/extensions/mpam.h>
23#include <lib/extensions/spe.h>
24#include <lib/extensions/sve.h>
25#include <lib/utils.h>
26#include <plat/common/platform.h>
Antonio Nino Diaz3c817f42018-03-21 10:49:27 +000027#include <smccc_helpers.h>
Achin Gupta7aea9082014-02-01 07:51:28 +000028
Achin Gupta7aea9082014-02-01 07:51:28 +000029
30/*******************************************************************************
31 * Context management library initialisation routine. This library is used by
32 * runtime services to share pointers to 'cpu_context' structures for the secure
33 * and non-secure states. Management of the structures and their associated
34 * memory is not done by the context management library e.g. the PSCI service
35 * manages the cpu context used for entry from and exit to the non-secure state.
36 * The Secure payload dispatcher service manages the context(s) corresponding to
37 * the secure state. It also uses this library to get access to the non-secure
38 * state cpu context pointers.
39 * Lastly, this library provides the api to make SP_EL3 point to the cpu context
40 * which will used for programming an entry into a lower EL. The same context
41 * will used to save state upon exception entry from that EL.
42 ******************************************************************************/
Daniel Boulby5753e492018-09-20 14:12:46 +010043void __init cm_init(void)
Achin Gupta7aea9082014-02-01 07:51:28 +000044{
45 /*
46 * The context management library has only global data to intialize, but
47 * that will be done when the BSS is zeroed out
48 */
49}
50
51/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +010052 * The following function initializes the cpu_context 'ctx' for
Andrew Thoelke4e126072014-06-04 21:10:52 +010053 * first use, and sets the initial entrypoint state as specified by the
54 * entry_point_info structure.
55 *
56 * The security state to initialize is determined by the SECURE attribute
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010057 * of the entry_point_info.
Andrew Thoelke4e126072014-06-04 21:10:52 +010058 *
Paul Beesley1fbc97b2019-01-11 18:26:51 +000059 * The EE and ST attributes are used to configure the endianness and secure
Soby Mathewb0082d22015-04-09 13:40:55 +010060 * timer availability for the new execution context.
Andrew Thoelke4e126072014-06-04 21:10:52 +010061 *
62 * To prepare the register state for entry call cm_prepare_el3_exit() and
63 * el3_exit(). For Secure-EL1 cm_prepare_el3_exit() is equivalent to
64 * cm_e1_sysreg_context_restore().
65 ******************************************************************************/
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +010066void cm_setup_context(cpu_context_t *ctx, const entry_point_info_t *ep)
Andrew Thoelke4e126072014-06-04 21:10:52 +010067{
Soby Mathewb0082d22015-04-09 13:40:55 +010068 unsigned int security_state;
Alexei Fedorov503bbf32019-08-13 15:17:53 +010069 uint32_t scr_el3;
Andrew Thoelke4e126072014-06-04 21:10:52 +010070 el3_state_t *state;
71 gp_regs_t *gp_regs;
Deepika Bhavnanib0f26022019-09-03 21:08:51 +030072 u_register_t sctlr_elx, actlr_elx;
Andrew Thoelke4e126072014-06-04 21:10:52 +010073
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000074 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +010075
Soby Mathewb0082d22015-04-09 13:40:55 +010076 security_state = GET_SECURITY_STATE(ep->h.attr);
77
Andrew Thoelke4e126072014-06-04 21:10:52 +010078 /* Clear any residual register values from the context */
Douglas Raillarda8954fc2017-01-26 15:54:44 +000079 zeromem(ctx, sizeof(*ctx));
Andrew Thoelke4e126072014-06-04 21:10:52 +010080
81 /*
David Cunadofee86532017-04-13 22:38:29 +010082 * SCR_EL3 was initialised during reset sequence in macro
83 * el3_arch_init_common. This code modifies the SCR_EL3 fields that
84 * affect the next EL.
85 *
86 * The following fields are initially set to zero and then updated to
87 * the required value depending on the state of the SPSR_EL3 and the
88 * Security state and entrypoint attributes of the next EL.
Andrew Thoelke4e126072014-06-04 21:10:52 +010089 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +000090 scr_el3 = (uint32_t)read_scr();
Andrew Thoelke4e126072014-06-04 21:10:52 +010091 scr_el3 &= ~(SCR_NS_BIT | SCR_RW_BIT | SCR_FIQ_BIT | SCR_IRQ_BIT |
92 SCR_ST_BIT | SCR_HCE_BIT);
David Cunadofee86532017-04-13 22:38:29 +010093 /*
94 * SCR_NS: Set the security state of the next EL.
95 */
Andrew Thoelke4e126072014-06-04 21:10:52 +010096 if (security_state != SECURE)
97 scr_el3 |= SCR_NS_BIT;
David Cunadofee86532017-04-13 22:38:29 +010098 /*
99 * SCR_EL3.RW: Set the execution state, AArch32 or AArch64, for next
100 * Exception level as specified by SPSR.
101 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100102 if (GET_RW(ep->spsr) == MODE_RW_64)
103 scr_el3 |= SCR_RW_BIT;
David Cunadofee86532017-04-13 22:38:29 +0100104 /*
105 * SCR_EL3.ST: Traps Secure EL1 accesses to the Counter-timer Physical
106 * Secure timer registers to EL3, from AArch64 state only, if specified
107 * by the entrypoint attributes.
108 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000109 if (EP_GET_ST(ep->h.attr) != 0U)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100110 scr_el3 |= SCR_ST_BIT;
111
Julius Wernerc51a2ec2018-08-28 14:45:43 -0700112#if !HANDLE_EA_EL3_FIRST
David Cunadofee86532017-04-13 22:38:29 +0100113 /*
114 * SCR_EL3.EA: Do not route External Abort and SError Interrupt External
115 * to EL3 when executing at a lower EL. When executing at EL3, External
116 * Aborts are taken to EL3.
117 */
Gerald Lejeune632d6df2016-03-22 09:29:23 +0100118 scr_el3 &= ~SCR_EA_BIT;
119#endif
120
Jeenu Viswambharanf00da742017-12-08 12:13:51 +0000121#if FAULT_INJECTION_SUPPORT
122 /* Enable fault injection from lower ELs */
123 scr_el3 |= SCR_FIEN_BIT;
124#endif
125
Antonio Nino Diaz594811b2019-01-31 11:58:00 +0000126#if !CTX_INCLUDE_PAUTH_REGS
127 /*
128 * If the pointer authentication registers aren't saved during world
129 * switches the value of the registers can be leaked from the Secure to
130 * the Non-secure world. To prevent this, rather than enabling pointer
131 * authentication everywhere, we only enable it in the Non-secure world.
132 *
133 * If the Secure world wants to use pointer authentication,
134 * CTX_INCLUDE_PAUTH_REGS must be set to 1.
135 */
136 if (security_state == NON_SECURE)
137 scr_el3 |= SCR_API_BIT | SCR_APK_BIT;
138#endif /* !CTX_INCLUDE_PAUTH_REGS */
139
Soby Mathew830f0ad2019-07-12 09:23:38 +0100140 /*
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100141 * Enable MTE support. Support is enabled unilaterally for the normal
142 * world, and only for the secure world when CTX_INCLUDE_MTE_REGS is
143 * set.
Soby Mathew830f0ad2019-07-12 09:23:38 +0100144 */
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100145#if CTX_INCLUDE_MTE_REGS
Justin Chadwell05e030e2019-09-20 09:13:14 +0100146 assert(get_armv8_5_mte_support() == MTE_IMPLEMENTED_ELX);
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100147 scr_el3 |= SCR_ATA_BIT;
148#else
Justin Chadwell05e030e2019-09-20 09:13:14 +0100149 unsigned int mte = get_armv8_5_mte_support();
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100150 if (mte == MTE_IMPLEMENTED_EL0) {
151 /*
152 * Can enable MTE across both worlds as no MTE registers are
153 * used
154 */
155 scr_el3 |= SCR_ATA_BIT;
156 } else if (mte == MTE_IMPLEMENTED_ELX && security_state == NON_SECURE) {
157 /*
158 * Can only enable MTE in Non-Secure world without register
159 * saving
160 */
161 scr_el3 |= SCR_ATA_BIT;
Soby Mathew830f0ad2019-07-12 09:23:38 +0100162 }
Justin Chadwell1c7c13a2019-07-18 14:25:33 +0100163#endif
Soby Mathew830f0ad2019-07-12 09:23:38 +0100164
Masahiro Yamada441bfdd2016-12-25 23:36:24 +0900165#ifdef IMAGE_BL31
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100166 /*
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000167 * SCR_EL3.IRQ, SCR_EL3.FIQ: Enable the physical FIQ and IRQ routing as
David Cunadofee86532017-04-13 22:38:29 +0100168 * indicated by the interrupt routing model for BL31.
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100169 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100170 scr_el3 |= get_scr_el3_from_routing_model(security_state);
Yatharth Kochar6c0566c2015-10-02 17:56:48 +0100171#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100172
173 /*
David Cunadofee86532017-04-13 22:38:29 +0100174 * SCR_EL3.HCE: Enable HVC instructions if next execution state is
175 * AArch64 and next EL is EL2, or if next execution state is AArch32 and
176 * next mode is Hyp.
177 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000178 if (((GET_RW(ep->spsr) == MODE_RW_64) && (GET_EL(ep->spsr) == MODE_EL2))
179 || ((GET_RW(ep->spsr) != MODE_RW_64)
180 && (GET_M32(ep->spsr) == MODE32_hyp))) {
David Cunadofee86532017-04-13 22:38:29 +0100181 scr_el3 |= SCR_HCE_BIT;
182 }
183
Achin Gupta023c1552019-10-11 14:44:05 +0100184 /* Enable S-EL2 if the next EL is EL2 and security state is secure */
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000185 if ((security_state == SECURE) && (GET_EL(ep->spsr) == MODE_EL2)) {
186 if (GET_RW(ep->spsr) != MODE_RW_64) {
187 ERROR("S-EL2 can not be used in AArch32.");
188 panic();
189 }
190
Achin Gupta023c1552019-10-11 14:44:05 +0100191 scr_el3 |= SCR_EEL2_BIT;
Artsem Artsemenkaa5334472019-11-26 16:40:31 +0000192 }
Achin Gupta023c1552019-10-11 14:44:05 +0100193
David Cunadofee86532017-04-13 22:38:29 +0100194 /*
195 * Initialise SCTLR_EL1 to the reset value corresponding to the target
196 * execution state setting all fields rather than relying of the hw.
197 * Some fields have architecturally UNKNOWN reset values and these are
198 * set to zero.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100199 *
David Cunadofee86532017-04-13 22:38:29 +0100200 * SCTLR.EE: Endianness is taken from the entrypoint attributes.
Andrew Thoelke4e126072014-06-04 21:10:52 +0100201 *
David Cunadofee86532017-04-13 22:38:29 +0100202 * SCTLR.M, SCTLR.C and SCTLR.I: These fields must be zero (as
203 * required by PSCI specification)
Andrew Thoelke4e126072014-06-04 21:10:52 +0100204 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000205 sctlr_elx = (EP_GET_EE(ep->h.attr) != 0U) ? SCTLR_EE_BIT : 0U;
Jens Wiklanderc93c9df2014-09-04 10:23:27 +0200206 if (GET_RW(ep->spsr) == MODE_RW_64)
207 sctlr_elx |= SCTLR_EL1_RES1;
Soby Mathewa993c422016-09-29 14:15:57 +0100208 else {
Soby Mathewa993c422016-09-29 14:15:57 +0100209 /*
David Cunadofee86532017-04-13 22:38:29 +0100210 * If the target execution state is AArch32 then the following
211 * fields need to be set.
212 *
213 * SCTRL_EL1.nTWE: Set to one so that EL0 execution of WFE
214 * instructions are not trapped to EL1.
215 *
216 * SCTLR_EL1.nTWI: Set to one so that EL0 execution of WFI
217 * instructions are not trapped to EL1.
218 *
219 * SCTLR_EL1.CP15BEN: Set to one to enable EL0 execution of the
220 * CP15DMB, CP15DSB, and CP15ISB instructions.
Soby Mathewa993c422016-09-29 14:15:57 +0100221 */
David Cunadofee86532017-04-13 22:38:29 +0100222 sctlr_elx |= SCTLR_AARCH32_EL1_RES1 | SCTLR_CP15BEN_BIT
223 | SCTLR_NTWI_BIT | SCTLR_NTWE_BIT;
Soby Mathewa993c422016-09-29 14:15:57 +0100224 }
225
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000226#if ERRATA_A75_764081
227 /*
228 * If workaround of errata 764081 for Cortex-A75 is used then set
229 * SCTLR_EL1.IESB to enable Implicit Error Synchronization Barrier.
230 */
231 sctlr_elx |= SCTLR_IESB_BIT;
232#endif
233
David Cunadofee86532017-04-13 22:38:29 +0100234 /*
235 * Store the initialised SCTLR_EL1 value in the cpu_context - SCTLR_EL2
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000236 * and other EL2 registers are set up by cm_prepare_ns_entry() as they
David Cunadofee86532017-04-13 22:38:29 +0100237 * are not part of the stored cpu_context.
238 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100239 write_ctx_reg(get_sysregs_ctx(ctx), CTX_SCTLR_EL1, sctlr_elx);
240
Varun Wadekarb6dd0b32018-05-08 10:52:36 -0700241 /*
242 * Base the context ACTLR_EL1 on the current value, as it is
243 * implementation defined. The context restore process will write
244 * the value from the context to the actual register and can cause
245 * problems for processor cores that don't expect certain bits to
246 * be zero.
247 */
248 actlr_elx = read_actlr_el1();
249 write_ctx_reg((get_sysregs_ctx(ctx)), (CTX_ACTLR_EL1), (actlr_elx));
250
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100251 /*
252 * Populate EL3 state so that we've the right context
253 * before doing ERET
254 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100255 state = get_el3state_ctx(ctx);
256 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
257 write_ctx_reg(state, CTX_ELR_EL3, ep->pc);
258 write_ctx_reg(state, CTX_SPSR_EL3, ep->spsr);
259
260 /*
261 * Store the X0-X7 value from the entrypoint into the context
262 * Use memcpy as we are in control of the layout of the structures
263 */
264 gp_regs = get_gpregs_ctx(ctx);
265 memcpy(gp_regs, (void *)&ep->args, sizeof(aapcs64_params_t));
266}
267
268/*******************************************************************************
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000269 * Enable architecture extensions on first entry to Non-secure world.
270 * When EL2 is implemented but unused `el2_unused` is non-zero, otherwise
271 * it is zero.
272 ******************************************************************************/
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100273static void enable_extensions_nonsecure(bool el2_unused)
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000274{
275#if IMAGE_BL31
Dimitris Papastamos5bdbb472017-10-13 12:06:06 +0100276#if ENABLE_SPE_FOR_LOWER_ELS
277 spe_enable(el2_unused);
278#endif
Dimitris Papastamose08005a2017-10-12 13:02:29 +0100279
280#if ENABLE_AMU
281 amu_enable(el2_unused);
282#endif
David Cunadoce88eee2017-10-20 11:30:57 +0100283
284#if ENABLE_SVE_FOR_NS
285 sve_enable(el2_unused);
286#endif
Jeenu Viswambharan2da918c2018-07-31 16:13:33 +0100287
288#if ENABLE_MPAM_FOR_LOWER_ELS
289 mpam_enable(el2_unused);
290#endif
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000291#endif
292}
293
294/*******************************************************************************
Soby Mathewb0082d22015-04-09 13:40:55 +0100295 * The following function initializes the cpu_context for a CPU specified by
296 * its `cpu_idx` for first use, and sets the initial entrypoint state as
297 * specified by the entry_point_info structure.
298 ******************************************************************************/
299void cm_init_context_by_index(unsigned int cpu_idx,
300 const entry_point_info_t *ep)
301{
302 cpu_context_t *ctx;
303 ctx = cm_get_context_by_index(cpu_idx, GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100304 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100305}
306
307/*******************************************************************************
308 * The following function initializes the cpu_context for the current CPU
309 * for first use, and sets the initial entrypoint state as specified by the
310 * entry_point_info structure.
311 ******************************************************************************/
312void cm_init_my_context(const entry_point_info_t *ep)
313{
314 cpu_context_t *ctx;
315 ctx = cm_get_context(GET_SECURITY_STATE(ep->h.attr));
Antonio Nino Diaz28dce9e2018-05-22 10:09:10 +0100316 cm_setup_context(ctx, ep);
Soby Mathewb0082d22015-04-09 13:40:55 +0100317}
318
319/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100320 * Prepare the CPU system registers for first entry into secure or normal world
321 *
322 * If execution is requested to EL2 or hyp mode, SCTLR_EL2 is initialized
323 * If execution is requested to non-secure EL1 or svc mode, and the CPU supports
324 * EL2 then EL2 is disabled by configuring all necessary EL2 registers.
325 * For all entries, the EL1 registers are initialized from the cpu_context
326 ******************************************************************************/
327void cm_prepare_el3_exit(uint32_t security_state)
328{
dp-armee3457b2017-05-23 09:32:49 +0100329 uint32_t sctlr_elx, scr_el3, mdcr_el2;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100330 cpu_context_t *ctx = cm_get_context(security_state);
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100331 bool el2_unused = false;
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000332 uint64_t hcr_el2 = 0U;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100333
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000334 assert(ctx != NULL);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100335
336 if (security_state == NON_SECURE) {
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000337 scr_el3 = (uint32_t)read_ctx_reg(get_el3state_ctx(ctx),
338 CTX_SCR_EL3);
339 if ((scr_el3 & SCR_HCE_BIT) != 0U) {
Andrew Thoelke4e126072014-06-04 21:10:52 +0100340 /* Use SCTLR_EL1.EE value to initialise sctlr_el2 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000341 sctlr_elx = (uint32_t)read_ctx_reg(get_sysregs_ctx(ctx),
342 CTX_SCTLR_EL1);
Ken Kuang00eac152017-08-23 16:03:29 +0800343 sctlr_elx &= SCTLR_EE_BIT;
Andrew Thoelke4e126072014-06-04 21:10:52 +0100344 sctlr_elx |= SCTLR_EL2_RES1;
Louis Mayencourt78a0aed2019-02-20 12:11:41 +0000345#if ERRATA_A75_764081
346 /*
347 * If workaround of errata 764081 for Cortex-A75 is used
348 * then set SCTLR_EL2.IESB to enable Implicit Error
349 * Synchronization Barrier.
350 */
351 sctlr_elx |= SCTLR_IESB_BIT;
352#endif
Andrew Thoelke4e126072014-06-04 21:10:52 +0100353 write_sctlr_el2(sctlr_elx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000354 } else if (el_implemented(2) != EL_IMPL_NONE) {
Antonio Nino Diaz033b4bb2018-10-25 16:52:26 +0100355 el2_unused = true;
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000356
David Cunadofee86532017-04-13 22:38:29 +0100357 /*
358 * EL2 present but unused, need to disable safely.
359 * SCTLR_EL2 can be ignored in this case.
360 *
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100361 * Set EL2 register width appropriately: Set HCR_EL2
362 * field to match SCR_EL3.RW.
David Cunadofee86532017-04-13 22:38:29 +0100363 */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000364 if ((scr_el3 & SCR_RW_BIT) != 0U)
Jeenu Viswambharancbad6612018-08-15 14:29:29 +0100365 hcr_el2 |= HCR_RW_BIT;
366
367 /*
368 * For Armv8.3 pointer authentication feature, disable
369 * traps to EL2 when accessing key registers or using
370 * pointer authentication instructions from lower ELs.
371 */
372 hcr_el2 |= (HCR_API_BIT | HCR_APK_BIT);
373
374 write_hcr_el2(hcr_el2);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100375
David Cunadofee86532017-04-13 22:38:29 +0100376 /*
377 * Initialise CPTR_EL2 setting all fields rather than
378 * relying on the hw. All fields have architecturally
379 * UNKNOWN reset values.
380 *
381 * CPTR_EL2.TCPAC: Set to zero so that Non-secure EL1
382 * accesses to the CPACR_EL1 or CPACR from both
383 * Execution states do not trap to EL2.
384 *
385 * CPTR_EL2.TTA: Set to zero so that Non-secure System
386 * register accesses to the trace registers from both
387 * Execution states do not trap to EL2.
388 *
389 * CPTR_EL2.TFP: Set to zero so that Non-secure accesses
390 * to SIMD and floating-point functionality from both
391 * Execution states do not trap to EL2.
392 */
393 write_cptr_el2(CPTR_EL2_RESET_VAL &
394 ~(CPTR_EL2_TCPAC_BIT | CPTR_EL2_TTA_BIT
395 | CPTR_EL2_TFP_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100396
David Cunadofee86532017-04-13 22:38:29 +0100397 /*
Paul Beesley1fbc97b2019-01-11 18:26:51 +0000398 * Initialise CNTHCTL_EL2. All fields are
David Cunadofee86532017-04-13 22:38:29 +0100399 * architecturally UNKNOWN on reset and are set to zero
400 * except for field(s) listed below.
401 *
402 * CNTHCTL_EL2.EL1PCEN: Set to one to disable traps to
403 * Hyp mode of Non-secure EL0 and EL1 accesses to the
404 * physical timer registers.
405 *
406 * CNTHCTL_EL2.EL1PCTEN: Set to one to disable traps to
407 * Hyp mode of Non-secure EL0 and EL1 accesses to the
408 * physical counter registers.
409 */
410 write_cnthctl_el2(CNTHCTL_RESET_VAL |
411 EL1PCEN_BIT | EL1PCTEN_BIT);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100412
David Cunadofee86532017-04-13 22:38:29 +0100413 /*
414 * Initialise CNTVOFF_EL2 to zero as it resets to an
415 * architecturally UNKNOWN value.
416 */
Soby Mathewfeddfcf2014-08-29 14:41:58 +0100417 write_cntvoff_el2(0);
418
David Cunadofee86532017-04-13 22:38:29 +0100419 /*
420 * Set VPIDR_EL2 and VMPIDR_EL2 to match MIDR_EL1 and
421 * MPIDR_EL1 respectively.
422 */
Andrew Thoelke4e126072014-06-04 21:10:52 +0100423 write_vpidr_el2(read_midr_el1());
424 write_vmpidr_el2(read_mpidr_el1());
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000425
426 /*
David Cunadofee86532017-04-13 22:38:29 +0100427 * Initialise VTTBR_EL2. All fields are architecturally
428 * UNKNOWN on reset.
429 *
430 * VTTBR_EL2.VMID: Set to zero. Even though EL1&0 stage
431 * 2 address translation is disabled, cache maintenance
432 * operations depend on the VMID.
433 *
434 * VTTBR_EL2.BADDR: Set to zero as EL1&0 stage 2 address
435 * translation is disabled.
Sandrine Bailleux8b0eafe2015-11-25 17:00:44 +0000436 */
David Cunadofee86532017-04-13 22:38:29 +0100437 write_vttbr_el2(VTTBR_RESET_VAL &
438 ~((VTTBR_VMID_MASK << VTTBR_VMID_SHIFT)
439 | (VTTBR_BADDR_MASK << VTTBR_BADDR_SHIFT)));
440
David Cunado5f55e282016-10-31 17:37:34 +0000441 /*
David Cunadofee86532017-04-13 22:38:29 +0100442 * Initialise MDCR_EL2, setting all fields rather than
443 * relying on hw. Some fields are architecturally
444 * UNKNOWN on reset.
445 *
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100446 * MDCR_EL2.HLP: Set to one so that event counter
447 * overflow, that is recorded in PMOVSCLR_EL0[0-30],
448 * occurs on the increment that changes
449 * PMEVCNTR<n>_EL0[63] from 1 to 0, when ARMv8.5-PMU is
450 * implemented. This bit is RES0 in versions of the
451 * architecture earlier than ARMv8.5, setting it to 1
452 * doesn't have any effect on them.
453 *
454 * MDCR_EL2.TTRF: Set to zero so that access to Trace
455 * Filter Control register TRFCR_EL1 at EL1 is not
456 * trapped to EL2. This bit is RES0 in versions of
457 * the architecture earlier than ARMv8.4.
458 *
459 * MDCR_EL2.HPMD: Set to one so that event counting is
460 * prohibited at EL2. This bit is RES0 in versions of
461 * the architecture earlier than ARMv8.1, setting it
462 * to 1 doesn't have any effect on them.
463 *
464 * MDCR_EL2.TPMS: Set to zero so that accesses to
465 * Statistical Profiling control registers from EL1
466 * do not trap to EL2. This bit is RES0 when SPE is
467 * not implemented.
468 *
David Cunadofee86532017-04-13 22:38:29 +0100469 * MDCR_EL2.TDRA: Set to zero so that Non-secure EL0 and
470 * EL1 System register accesses to the Debug ROM
471 * registers are not trapped to EL2.
472 *
473 * MDCR_EL2.TDOSA: Set to zero so that Non-secure EL1
474 * System register accesses to the powerdown debug
475 * registers are not trapped to EL2.
476 *
477 * MDCR_EL2.TDA: Set to zero so that System register
478 * accesses to the debug registers do not trap to EL2.
479 *
480 * MDCR_EL2.TDE: Set to zero so that debug exceptions
481 * are not routed to EL2.
482 *
483 * MDCR_EL2.HPME: Set to zero to disable EL2 Performance
484 * Monitors.
485 *
486 * MDCR_EL2.TPM: Set to zero so that Non-secure EL0 and
487 * EL1 accesses to all Performance Monitors registers
488 * are not trapped to EL2.
489 *
490 * MDCR_EL2.TPMCR: Set to zero so that Non-secure EL0
491 * and EL1 accesses to the PMCR_EL0 or PMCR are not
492 * trapped to EL2.
493 *
494 * MDCR_EL2.HPMN: Set to value of PMCR_EL0.N which is the
495 * architecturally-defined reset value.
David Cunado5f55e282016-10-31 17:37:34 +0000496 */
Alexei Fedorov503bbf32019-08-13 15:17:53 +0100497 mdcr_el2 = ((MDCR_EL2_RESET_VAL | MDCR_EL2_HLP |
498 MDCR_EL2_HPMD) |
499 ((read_pmcr_el0() & PMCR_EL0_N_BITS)
500 >> PMCR_EL0_N_SHIFT)) &
501 ~(MDCR_EL2_TTRF | MDCR_EL2_TPMS |
502 MDCR_EL2_TDRA_BIT | MDCR_EL2_TDOSA_BIT |
503 MDCR_EL2_TDA_BIT | MDCR_EL2_TDE_BIT |
504 MDCR_EL2_HPME_BIT | MDCR_EL2_TPM_BIT |
505 MDCR_EL2_TPMCR_BIT);
dp-armee3457b2017-05-23 09:32:49 +0100506
dp-armee3457b2017-05-23 09:32:49 +0100507 write_mdcr_el2(mdcr_el2);
508
David Cunadoc14b08e2016-11-25 00:21:59 +0000509 /*
David Cunadofee86532017-04-13 22:38:29 +0100510 * Initialise HSTR_EL2. All fields are architecturally
511 * UNKNOWN on reset.
512 *
513 * HSTR_EL2.T<n>: Set all these fields to zero so that
514 * Non-secure EL0 or EL1 accesses to System registers
515 * do not trap to EL2.
David Cunadoc14b08e2016-11-25 00:21:59 +0000516 */
David Cunadofee86532017-04-13 22:38:29 +0100517 write_hstr_el2(HSTR_EL2_RESET_VAL & ~(HSTR_EL2_T_MASK));
David Cunadoc14b08e2016-11-25 00:21:59 +0000518 /*
David Cunadofee86532017-04-13 22:38:29 +0100519 * Initialise CNTHP_CTL_EL2. All fields are
520 * architecturally UNKNOWN on reset.
521 *
522 * CNTHP_CTL_EL2:ENABLE: Set to zero to disable the EL2
523 * physical timer and prevent timer interrupts.
David Cunadoc14b08e2016-11-25 00:21:59 +0000524 */
David Cunadofee86532017-04-13 22:38:29 +0100525 write_cnthp_ctl_el2(CNTHP_CTL_RESET_VAL &
526 ~(CNTHP_CTL_ENABLE_BIT));
Andrew Thoelke4e126072014-06-04 21:10:52 +0100527 }
Dimitris Papastamos1e6f93e2017-11-07 09:55:29 +0000528 enable_extensions_nonsecure(el2_unused);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100529 }
530
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100531 cm_el1_sysregs_context_restore(security_state);
532 cm_set_next_eret_context(security_state);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100533}
534
535/*******************************************************************************
Soby Mathew2ed46e92014-07-04 16:02:26 +0100536 * The next four functions are used by runtime services to save and restore
537 * EL1 context on the 'cpu_context' structure for the specified security
Achin Gupta7aea9082014-02-01 07:51:28 +0000538 * state.
539 ******************************************************************************/
Achin Gupta7aea9082014-02-01 07:51:28 +0000540void cm_el1_sysregs_context_save(uint32_t security_state)
541{
Dan Handleye2712bc2014-04-10 15:37:22 +0100542 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000543
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100544 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000545 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000546
547 el1_sysregs_context_save(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100548
549#if IMAGE_BL31
550 if (security_state == SECURE)
551 PUBLISH_EVENT(cm_exited_secure_world);
552 else
553 PUBLISH_EVENT(cm_exited_normal_world);
554#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000555}
556
557void cm_el1_sysregs_context_restore(uint32_t security_state)
558{
Dan Handleye2712bc2014-04-10 15:37:22 +0100559 cpu_context_t *ctx;
Achin Gupta7aea9082014-02-01 07:51:28 +0000560
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100561 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000562 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000563
564 el1_sysregs_context_restore(get_sysregs_ctx(ctx));
Dimitris Papastamosa7921b92017-10-13 15:27:58 +0100565
566#if IMAGE_BL31
567 if (security_state == SECURE)
568 PUBLISH_EVENT(cm_entering_secure_world);
569 else
570 PUBLISH_EVENT(cm_entering_normal_world);
571#endif
Achin Gupta7aea9082014-02-01 07:51:28 +0000572}
573
574/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100575 * This function populates ELR_EL3 member of 'cpu_context' pertaining to the
576 * given security state with the given entrypoint
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000577 ******************************************************************************/
Soby Mathewa0fedc42016-06-16 14:52:04 +0100578void cm_set_elr_el3(uint32_t security_state, uintptr_t entrypoint)
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000579{
Dan Handleye2712bc2014-04-10 15:37:22 +0100580 cpu_context_t *ctx;
581 el3_state_t *state;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000582
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100583 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000584 assert(ctx != NULL);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000585
Andrew Thoelke4e126072014-06-04 21:10:52 +0100586 /* Populate EL3 state so that ERET jumps to the correct entry */
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000587 state = get_el3state_ctx(ctx);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000588 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000589}
590
591/*******************************************************************************
Andrew Thoelke4e126072014-06-04 21:10:52 +0100592 * This function populates ELR_EL3 and SPSR_EL3 members of 'cpu_context'
593 * pertaining to the given security state
Achin Gupta607084e2014-02-09 18:24:19 +0000594 ******************************************************************************/
Andrew Thoelke4e126072014-06-04 21:10:52 +0100595void cm_set_elr_spsr_el3(uint32_t security_state,
Soby Mathewa0fedc42016-06-16 14:52:04 +0100596 uintptr_t entrypoint, uint32_t spsr)
Achin Gupta607084e2014-02-09 18:24:19 +0000597{
Dan Handleye2712bc2014-04-10 15:37:22 +0100598 cpu_context_t *ctx;
599 el3_state_t *state;
Achin Gupta607084e2014-02-09 18:24:19 +0000600
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100601 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000602 assert(ctx != NULL);
Achin Gupta607084e2014-02-09 18:24:19 +0000603
604 /* Populate EL3 state so that ERET jumps to the correct entry */
605 state = get_el3state_ctx(ctx);
606 write_ctx_reg(state, CTX_ELR_EL3, entrypoint);
Andrew Thoelke4e126072014-06-04 21:10:52 +0100607 write_ctx_reg(state, CTX_SPSR_EL3, spsr);
Achin Gupta607084e2014-02-09 18:24:19 +0000608}
609
610/*******************************************************************************
Achin Gupta27b895e2014-05-04 18:38:28 +0100611 * This function updates a single bit in the SCR_EL3 member of the 'cpu_context'
612 * pertaining to the given security state using the value and bit position
613 * specified in the parameters. It preserves all other bits.
614 ******************************************************************************/
615void cm_write_scr_el3_bit(uint32_t security_state,
616 uint32_t bit_pos,
617 uint32_t value)
618{
619 cpu_context_t *ctx;
620 el3_state_t *state;
621 uint32_t scr_el3;
622
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100623 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000624 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100625
626 /* Ensure that the bit position is a valid one */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000627 assert(((1U << bit_pos) & SCR_VALID_BIT_MASK) != 0U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100628
629 /* Ensure that the 'value' is only a bit wide */
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000630 assert(value <= 1U);
Achin Gupta27b895e2014-05-04 18:38:28 +0100631
632 /*
633 * Get the SCR_EL3 value from the cpu context, clear the desired bit
634 * and set it to its new value.
635 */
636 state = get_el3state_ctx(ctx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000637 scr_el3 = (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
638 scr_el3 &= ~(1U << bit_pos);
Achin Gupta27b895e2014-05-04 18:38:28 +0100639 scr_el3 |= value << bit_pos;
640 write_ctx_reg(state, CTX_SCR_EL3, scr_el3);
641}
642
643/*******************************************************************************
644 * This function retrieves SCR_EL3 member of 'cpu_context' pertaining to the
645 * given security state.
646 ******************************************************************************/
647uint32_t cm_get_scr_el3(uint32_t security_state)
648{
649 cpu_context_t *ctx;
650 el3_state_t *state;
651
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100652 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000653 assert(ctx != NULL);
Achin Gupta27b895e2014-05-04 18:38:28 +0100654
655 /* Populate EL3 state so that ERET jumps to the correct entry */
656 state = get_el3state_ctx(ctx);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000657 return (uint32_t)read_ctx_reg(state, CTX_SCR_EL3);
Achin Gupta27b895e2014-05-04 18:38:28 +0100658}
659
660/*******************************************************************************
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000661 * This function is used to program the context that's used for exception
662 * return. This initializes the SP_EL3 to a pointer to a 'cpu_context' set for
663 * the required security state
Achin Gupta7aea9082014-02-01 07:51:28 +0000664 ******************************************************************************/
665void cm_set_next_eret_context(uint32_t security_state)
666{
Dan Handleye2712bc2014-04-10 15:37:22 +0100667 cpu_context_t *ctx;
Jeenu Viswambharancaa84932014-02-06 10:36:15 +0000668
Andrew Thoelkea2f65532014-05-14 17:09:32 +0100669 ctx = cm_get_context(security_state);
Antonio Nino Diaz864ca6f2018-10-31 15:25:35 +0000670 assert(ctx != NULL);
Achin Gupta7aea9082014-02-01 07:51:28 +0000671
Andrew Thoelke4e126072014-06-04 21:10:52 +0100672 cm_set_next_context(ctx);
Achin Gupta7aea9082014-02-01 07:51:28 +0000673}