Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 1 | /* |
Dan Handley | e83b0ca | 2014-01-14 18:17:09 +0000 | [diff] [blame] | 2 | * Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 3 | * |
| 4 | * Redistribution and use in source and binary forms, with or without |
| 5 | * modification, are permitted provided that the following conditions are met: |
| 6 | * |
| 7 | * Redistributions of source code must retain the above copyright notice, this |
| 8 | * list of conditions and the following disclaimer. |
| 9 | * |
| 10 | * Redistributions in binary form must reproduce the above copyright notice, |
| 11 | * this list of conditions and the following disclaimer in the documentation |
| 12 | * and/or other materials provided with the distribution. |
| 13 | * |
| 14 | * Neither the name of ARM nor the names of its contributors may be used |
| 15 | * to endorse or promote products derived from this software without specific |
| 16 | * prior written permission. |
| 17 | * |
| 18 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| 19 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| 20 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
| 21 | * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
| 22 | * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
| 23 | * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
| 24 | * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
| 25 | * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
| 26 | * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
| 27 | * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| 28 | * POSSIBILITY OF SUCH DAMAGE. |
| 29 | */ |
| 30 | |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 31 | #include <arch.h> |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 32 | #include <asm_macros.S> |
Dan Handley | 2bd4ef2 | 2014-04-09 13:14:54 +0100 | [diff] [blame] | 33 | #include <bl_common.h> |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 34 | |
| 35 | .globl bl31_entrypoint |
| 36 | |
| 37 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 38 | /* ----------------------------------------------------- |
| 39 | * bl31_entrypoint() is the cold boot entrypoint, |
| 40 | * executed only by the primary cpu. |
| 41 | * ----------------------------------------------------- |
| 42 | */ |
| 43 | |
Andrew Thoelke | 38bde41 | 2014-03-18 13:46:55 +0000 | [diff] [blame] | 44 | func bl31_entrypoint |
Vikram Kanigiri | da56743 | 2014-04-15 18:08:08 +0100 | [diff] [blame] | 45 | /* --------------------------------------------------------------- |
| 46 | * Preceding bootloader has populated x0 with a pointer to a |
| 47 | * 'bl31_params' structure & x1 with a pointer to platform |
| 48 | * specific structure |
| 49 | * --------------------------------------------------------------- |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 50 | */ |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 51 | #if !RESET_TO_BL31 |
Vikram Kanigiri | a3a5e4a | 2014-05-15 18:27:15 +0100 | [diff] [blame] | 52 | mov x20, x0 |
| 53 | mov x21, x1 |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 54 | #else |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 55 | /* --------------------------------------------- |
| 56 | * Set the CPU endianness before doing anything |
| 57 | * that might involve memory reads or writes. |
| 58 | * --------------------------------------------- |
| 59 | */ |
| 60 | mrs x0, sctlr_el3 |
| 61 | bic x0, x0, #SCTLR_EE_BIT |
| 62 | msr sctlr_el3, x0 |
| 63 | isb |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 64 | |
| 65 | /* ----------------------------------------------------- |
| 66 | * Perform any processor specific actions upon reset |
| 67 | * e.g. cache, tlb invalidations etc. Override the |
| 68 | * Boot ROM(BL0) programming sequence |
| 69 | * ----------------------------------------------------- |
| 70 | */ |
| 71 | bl cpu_reset_handler |
| 72 | #endif |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 73 | /* --------------------------------------------- |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 74 | * Enable the instruction cache, stack pointer |
| 75 | * and data access alignment checks |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 76 | * --------------------------------------------- |
| 77 | */ |
Achin Gupta | 9f09835 | 2014-07-18 18:38:28 +0100 | [diff] [blame] | 78 | mov x1, #(SCTLR_I_BIT | SCTLR_A_BIT | SCTLR_SA_BIT) |
| 79 | mrs x0, sctlr_el3 |
| 80 | orr x0, x0, x1 |
| 81 | msr sctlr_el3, x0 |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 82 | isb |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 83 | |
| 84 | /* --------------------------------------------- |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 85 | * Initialise cpu_data early to enable crash |
| 86 | * reporting to have access to crash stack. |
| 87 | * Since crash reporting depends on cpu_data to |
| 88 | * report the unhandled exception, not |
| 89 | * doing so can lead to recursive exceptions due |
| 90 | * to a NULL TPIDR_EL3 |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 91 | * --------------------------------------------- |
| 92 | */ |
Soby Mathew | c1adbbc | 2014-06-25 10:07:40 +0100 | [diff] [blame] | 93 | bl init_cpu_data_ptr |
| 94 | |
| 95 | /* --------------------------------------------- |
| 96 | * Set the exception vector. |
| 97 | * --------------------------------------------- |
| 98 | */ |
Andrew Thoelke | 4d2d553 | 2014-06-02 12:38:12 +0100 | [diff] [blame] | 99 | adr x1, runtime_exceptions |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 100 | msr vbar_el3, x1 |
Achin Gupta | ed1744e | 2014-08-04 23:13:10 +0100 | [diff] [blame] | 101 | isb |
| 102 | |
| 103 | /* --------------------------------------------- |
| 104 | * Enable the SError interrupt now that the |
| 105 | * exception vectors have been setup. |
| 106 | * --------------------------------------------- |
| 107 | */ |
| 108 | msr daifclr, #DAIF_ABT_BIT |
Sandrine Bailleux | c10bd2c | 2013-11-12 16:41:16 +0000 | [diff] [blame] | 109 | |
Harry Liebel | 4f60368 | 2014-01-14 18:11:48 +0000 | [diff] [blame] | 110 | /* --------------------------------------------------------------------- |
| 111 | * The initial state of the Architectural feature trap register |
| 112 | * (CPTR_EL3) is unknown and it must be set to a known state. All |
| 113 | * feature traps are disabled. Some bits in this register are marked as |
| 114 | * Reserved and should not be modified. |
| 115 | * |
| 116 | * CPTR_EL3.TCPAC: This causes a direct access to the CPACR_EL1 from EL1 |
| 117 | * or the CPTR_EL2 from EL2 to trap to EL3 unless it is trapped at EL2. |
| 118 | * CPTR_EL3.TTA: This causes access to the Trace functionality to trap |
| 119 | * to EL3 when executed from EL0, EL1, EL2, or EL3. If system register |
| 120 | * access to trace functionality is not supported, this bit is RES0. |
| 121 | * CPTR_EL3.TFP: This causes instructions that access the registers |
| 122 | * associated with Floating Point and Advanced SIMD execution to trap |
| 123 | * to EL3 when executed from any exception level, unless trapped to EL1 |
| 124 | * or EL2. |
| 125 | * --------------------------------------------------------------------- |
| 126 | */ |
| 127 | mrs x1, cptr_el3 |
| 128 | bic w1, w1, #TCPAC_BIT |
| 129 | bic w1, w1, #TTA_BIT |
| 130 | bic w1, w1, #TFP_BIT |
| 131 | msr cptr_el3, x1 |
| 132 | |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 133 | #if RESET_TO_BL31 |
Vikram Kanigiri | cf79bf5 | 2014-06-02 14:59:00 +0100 | [diff] [blame] | 134 | /* ------------------------------------------------------- |
| 135 | * Will not return from this macro if it is a warm boot. |
| 136 | * ------------------------------------------------------- |
| 137 | */ |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 138 | wait_for_entrypoint |
| 139 | bl platform_mem_init |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 140 | #endif |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 141 | |
Sandrine Bailleux | 65f546a | 2013-11-28 09:43:06 +0000 | [diff] [blame] | 142 | /* --------------------------------------------- |
| 143 | * Zero out NOBITS sections. There are 2 of them: |
| 144 | * - the .bss section; |
| 145 | * - the coherent memory section. |
| 146 | * --------------------------------------------- |
| 147 | */ |
| 148 | ldr x0, =__BSS_START__ |
| 149 | ldr x1, =__BSS_SIZE__ |
| 150 | bl zeromem16 |
| 151 | |
| 152 | ldr x0, =__COHERENT_RAM_START__ |
| 153 | ldr x1, =__COHERENT_RAM_UNALIGNED_SIZE__ |
| 154 | bl zeromem16 |
| 155 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 156 | /* --------------------------------------------- |
| 157 | * Use SP_EL0 for the C runtime stack. |
| 158 | * --------------------------------------------- |
| 159 | */ |
| 160 | msr spsel, #0 |
| 161 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 162 | /* -------------------------------------------- |
Achin Gupta | f4a9709 | 2014-06-25 19:26:22 +0100 | [diff] [blame] | 163 | * Allocate a stack whose memory will be marked |
| 164 | * as Normal-IS-WBWA when the MMU is enabled. |
| 165 | * There is no risk of reading stale stack |
| 166 | * memory after enabling the MMU as only the |
| 167 | * primary cpu is running at the moment. |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 168 | * -------------------------------------------- |
| 169 | */ |
Andrew Thoelke | f977ed8 | 2014-04-28 12:32:02 +0100 | [diff] [blame] | 170 | mrs x0, mpidr_el1 |
Achin Gupta | f4a9709 | 2014-06-25 19:26:22 +0100 | [diff] [blame] | 171 | bl platform_set_stack |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 172 | |
| 173 | /* --------------------------------------------- |
| 174 | * Perform platform specific early arch. setup |
| 175 | * --------------------------------------------- |
| 176 | */ |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 177 | #if RESET_TO_BL31 |
| 178 | mov x0, 0 |
| 179 | mov x1, 0 |
| 180 | #else |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 181 | mov x0, x20 |
| 182 | mov x1, x21 |
Vikram Kanigiri | 9637745 | 2014-04-24 11:02:16 +0100 | [diff] [blame] | 183 | #endif |
| 184 | |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 185 | bl bl31_early_platform_setup |
| 186 | bl bl31_plat_arch_setup |
| 187 | |
| 188 | /* --------------------------------------------- |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 189 | * Jump to main function. |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 190 | * --------------------------------------------- |
| 191 | */ |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 192 | bl bl31_main |
Achin Gupta | b739f22 | 2014-01-18 16:50:09 +0000 | [diff] [blame] | 193 | |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 194 | b el3_exit |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 195 | |
| 196 | _panic: |
Jeenu Viswambharan | caa8493 | 2014-02-06 10:36:15 +0000 | [diff] [blame] | 197 | wfi |
Achin Gupta | 4f6ad66 | 2013-10-25 09:08:21 +0100 | [diff] [blame] | 198 | b _panic |