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Yann Gautier4b0c72a2018-07-16 10:54:09 +02001/*
Yann Gautier8f268c82020-02-26 13:39:44 +01002 * Copyright (c) 2015-2020, ARM Limited and Contributors. All rights reserved.
Yann Gautier4b0c72a2018-07-16 10:54:09 +02003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7#ifndef STM32MP1_DEF_H
8#define STM32MP1_DEF_H
9
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010#include <common/tbbr/tbbr_img_def.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010011#include <drivers/st/stm32mp1_rcc.h>
12#include <dt-bindings/clock/stm32mp1-clks.h>
13#include <dt-bindings/reset/stm32mp1-resets.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000014#include <lib/utils_def.h>
15#include <lib/xlat_tables/xlat_tables_defs.h>
Yann Gautier4b0c72a2018-07-16 10:54:09 +020016
Julius Werner53456fc2019-07-09 13:49:11 -070017#ifndef __ASSEMBLER__
Yann Gautier091eab52019-06-04 18:06:34 +020018#include <drivers/st/bsec.h>
Yann Gautierb5d2ed42019-02-14 11:13:50 +010019#include <drivers/st/stm32mp1_clk.h>
20
Yann Gautier57e282b2019-01-07 11:17:24 +010021#include <boot_api.h>
Lionel Debieve7bd96f42019-09-03 12:22:23 +020022#include <stm32mp_auth.h>
Yann Gautieree8f5422019-02-14 11:13:25 +010023#include <stm32mp_common.h>
24#include <stm32mp_dt.h>
Yann Gautiere4a3c352019-02-14 10:53:33 +010025#include <stm32mp_shres_helpers.h>
Yann Gautierc7374052019-06-04 18:02:37 +020026#include <stm32mp1_dbgmcu.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010027#include <stm32mp1_private.h>
Etienne Carriere316d6342019-12-02 10:08:48 +010028#include <stm32mp1_shared_resources.h>
Yann Gautier57e282b2019-01-07 11:17:24 +010029#endif
30
Yann Gautier4b0c72a2018-07-16 10:54:09 +020031/*******************************************************************************
Yann Gautierc7374052019-06-04 18:02:37 +020032 * CHIP ID
33 ******************************************************************************/
34#define STM32MP157C_PART_NB U(0x05000000)
35#define STM32MP157A_PART_NB U(0x05000001)
36#define STM32MP153C_PART_NB U(0x05000024)
37#define STM32MP153A_PART_NB U(0x05000025)
38#define STM32MP151C_PART_NB U(0x0500002E)
39#define STM32MP151A_PART_NB U(0x0500002F)
40
41#define STM32MP1_REV_B U(0x2000)
42
43/*******************************************************************************
44 * PACKAGE ID
45 ******************************************************************************/
46#define PKG_AA_LFBGA448 U(4)
47#define PKG_AB_LFBGA354 U(3)
48#define PKG_AC_TFBGA361 U(2)
49#define PKG_AD_TFBGA257 U(1)
50
51/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +020052 * STM32MP1 memory map related constants
53 ******************************************************************************/
Lionel Debieve7bd96f42019-09-03 12:22:23 +020054#define STM32MP_ROM_BASE U(0x00000000)
55#define STM32MP_ROM_SIZE U(0x00020000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020056
Yann Gautiera2e2a302019-02-14 11:13:39 +010057#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
58#define STM32MP_SYSRAM_SIZE U(0x00040000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020059
Etienne Carriere72369b12019-12-08 08:17:56 +010060#define STM32MP_NS_SYSRAM_SIZE PAGE_SIZE
61#define STM32MP_NS_SYSRAM_BASE (STM32MP_SYSRAM_BASE + \
62 STM32MP_SYSRAM_SIZE - \
63 STM32MP_NS_SYSRAM_SIZE)
64
Etienne Carriere34f0e932020-07-16 17:36:18 +020065#define STM32MP_SCMI_NS_SHM_BASE STM32MP_NS_SYSRAM_BASE
66#define STM32MP_SCMI_NS_SHM_SIZE STM32MP_NS_SYSRAM_SIZE
67
Etienne Carriere72369b12019-12-08 08:17:56 +010068#define STM32MP_SEC_SYSRAM_BASE STM32MP_SYSRAM_BASE
69#define STM32MP_SEC_SYSRAM_SIZE (STM32MP_SYSRAM_SIZE - \
70 STM32MP_NS_SYSRAM_SIZE)
71
Yann Gautier4b0c72a2018-07-16 10:54:09 +020072/* DDR configuration */
Yann Gautiera2e2a302019-02-14 11:13:39 +010073#define STM32MP_DDR_BASE U(0xC0000000)
74#define STM32MP_DDR_MAX_SIZE U(0x40000000) /* Max 1GB */
Yann Gautierb3386f72019-04-19 09:41:01 +020075#ifdef AARCH32_SP_OPTEE
76#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
77#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
Yann Gautier8f268c82020-02-26 13:39:44 +010078#else
79#define STM32MP_DDR_S_SIZE U(0)
80#define STM32MP_DDR_SHMEM_SIZE U(0)
Yann Gautierb3386f72019-04-19 09:41:01 +020081#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +020082
83/* DDR power initializations */
Julius Werner53456fc2019-07-09 13:49:11 -070084#ifndef __ASSEMBLER__
Yann Gautier4b0c72a2018-07-16 10:54:09 +020085enum ddr_type {
86 STM32MP_DDR3,
87 STM32MP_LPDDR2,
Yann Gautier917a00c2019-04-16 16:20:58 +020088 STM32MP_LPDDR3
Yann Gautier4b0c72a2018-07-16 10:54:09 +020089};
90#endif
91
92/* Section used inside TF binaries */
Nicolas Le Bayon07084412019-09-27 11:05:31 +020093#define STM32MP_PARAM_LOAD_SIZE U(0x00002400) /* 9 KB for param */
Yann Gautier4b0c72a2018-07-16 10:54:09 +020094/* 256 Octets reserved for header */
Yann Gautiera2e2a302019-02-14 11:13:39 +010095#define STM32MP_HEADER_SIZE U(0x00000100)
Yann Gautier4b0c72a2018-07-16 10:54:09 +020096
Etienne Carriere72369b12019-12-08 08:17:56 +010097#define STM32MP_BINARY_BASE (STM32MP_SEC_SYSRAM_BASE + \
Yann Gautiera2e2a302019-02-14 11:13:39 +010098 STM32MP_PARAM_LOAD_SIZE + \
99 STM32MP_HEADER_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200100
Etienne Carriere72369b12019-12-08 08:17:56 +0100101#define STM32MP_BINARY_SIZE (STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100102 (STM32MP_PARAM_LOAD_SIZE + \
103 STM32MP_HEADER_SIZE))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200104
Yann Gautierb3386f72019-04-19 09:41:01 +0200105#ifdef AARCH32_SP_OPTEE
106#define STM32MP_BL32_SIZE U(0)
107
Etienne Carriere72369b12019-12-08 08:17:56 +0100108#define STM32MP_OPTEE_BASE STM32MP_SEC_SYSRAM_BASE
Yann Gautierb3386f72019-04-19 09:41:01 +0200109
110#define STM32MP_OPTEE_SIZE (STM32MP_DTB_BASE - \
111 STM32MP_OPTEE_BASE)
112#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200113#if STACK_PROTECTOR_ENABLED
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200114#define STM32MP_BL32_SIZE U(0x00012000) /* 72 KB for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200115#else
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200116#define STM32MP_BL32_SIZE U(0x00011000) /* 68 KB for BL32 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200117#endif
Yann Gautierb3386f72019-04-19 09:41:01 +0200118#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200119
Etienne Carriere72369b12019-12-08 08:17:56 +0100120#define STM32MP_BL32_BASE (STM32MP_SEC_SYSRAM_BASE + \
121 STM32MP_SEC_SYSRAM_SIZE - \
Yann Gautiera2e2a302019-02-14 11:13:39 +0100122 STM32MP_BL32_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200123
Yann Gautierb3386f72019-04-19 09:41:01 +0200124#ifdef AARCH32_SP_OPTEE
125#if STACK_PROTECTOR_ENABLED
Lionel Debieve402a46b2019-11-04 12:28:15 +0100126#define STM32MP_BL2_SIZE U(0x0001A000) /* 100 KB for BL2 */
Yann Gautierb3386f72019-04-19 09:41:01 +0200127#else
Lionel Debieve402a46b2019-11-04 12:28:15 +0100128#define STM32MP_BL2_SIZE U(0x00018000) /* 92 KB for BL2 */
Yann Gautierb3386f72019-04-19 09:41:01 +0200129#endif
130#else
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200131#if STACK_PROTECTOR_ENABLED
Lionel Debieve402a46b2019-11-04 12:28:15 +0100132#define STM32MP_BL2_SIZE U(0x00019000) /* 96 KB for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200133#else
Lionel Debieve402a46b2019-11-04 12:28:15 +0100134#define STM32MP_BL2_SIZE U(0x00017000) /* 88 KB for BL2 */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200135#endif
Yann Gautierb3386f72019-04-19 09:41:01 +0200136#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200137
Yann Gautiera2e2a302019-02-14 11:13:39 +0100138#define STM32MP_BL2_BASE (STM32MP_BL32_BASE - \
139 STM32MP_BL2_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200140
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200141/* BL2 and BL32/sp_min require 4 tables */
142#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200143
144/*
145 * MAX_MMAP_REGIONS is usually:
146 * BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
147 */
Yann Gautier9d135e42018-07-16 19:36:06 +0200148#if defined(IMAGE_BL2)
149 #define MAX_MMAP_REGIONS 11
150#endif
151#if defined(IMAGE_BL32)
152 #define MAX_MMAP_REGIONS 6
153#endif
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200154
155/* DTB initialization value */
Nicolas Le Bayon07084412019-09-27 11:05:31 +0200156#define STM32MP_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200157
Yann Gautiera2e2a302019-02-14 11:13:39 +0100158#define STM32MP_DTB_BASE (STM32MP_BL2_BASE - \
159 STM32MP_DTB_SIZE)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200160
Yann Gautiera2e2a302019-02-14 11:13:39 +0100161#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200162
Lionel Debieve402a46b2019-11-04 12:28:15 +0100163/* Define maximum page size for NAND devices */
164#define PLATFORM_MTD_MAX_PAGE_SIZE U(0x1000)
165
166/*******************************************************************************
167 * STM32MP1 RAW partition offset for MTD devices
168 ******************************************************************************/
Lionel Debievecb0dbc42019-09-25 09:11:31 +0200169#define STM32MP_NOR_BL33_OFFSET U(0x00080000)
170#ifdef AARCH32_SP_OPTEE
171#define STM32MP_NOR_TEEH_OFFSET U(0x00280000)
172#define STM32MP_NOR_TEED_OFFSET U(0x002C0000)
173#define STM32MP_NOR_TEEX_OFFSET U(0x00300000)
174#endif
175
Lionel Debieve402a46b2019-11-04 12:28:15 +0100176#define STM32MP_NAND_BL33_OFFSET U(0x00200000)
177#ifdef AARCH32_SP_OPTEE
178#define STM32MP_NAND_TEEH_OFFSET U(0x00600000)
179#define STM32MP_NAND_TEED_OFFSET U(0x00680000)
180#define STM32MP_NAND_TEEX_OFFSET U(0x00700000)
181#endif
182
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200183/*******************************************************************************
184 * STM32MP1 device/io map related constants (used for MMU)
185 ******************************************************************************/
186#define STM32MP1_DEVICE1_BASE U(0x40000000)
187#define STM32MP1_DEVICE1_SIZE U(0x40000000)
188
189#define STM32MP1_DEVICE2_BASE U(0x80000000)
190#define STM32MP1_DEVICE2_SIZE U(0x40000000)
191
192/*******************************************************************************
193 * STM32MP1 RCC
194 ******************************************************************************/
195#define RCC_BASE U(0x50000000)
196
197/*******************************************************************************
198 * STM32MP1 PWR
199 ******************************************************************************/
200#define PWR_BASE U(0x50001000)
201
202/*******************************************************************************
Yann Gautier038bff22019-01-17 19:17:47 +0100203 * STM32MP1 GPIO
204 ******************************************************************************/
205#define GPIOA_BASE U(0x50002000)
206#define GPIOB_BASE U(0x50003000)
207#define GPIOC_BASE U(0x50004000)
208#define GPIOD_BASE U(0x50005000)
209#define GPIOE_BASE U(0x50006000)
210#define GPIOF_BASE U(0x50007000)
211#define GPIOG_BASE U(0x50008000)
212#define GPIOH_BASE U(0x50009000)
213#define GPIOI_BASE U(0x5000A000)
214#define GPIOJ_BASE U(0x5000B000)
215#define GPIOK_BASE U(0x5000C000)
216#define GPIOZ_BASE U(0x54004000)
217#define GPIO_BANK_OFFSET U(0x1000)
218
219/* Bank IDs used in GPIO driver API */
220#define GPIO_BANK_A U(0)
221#define GPIO_BANK_B U(1)
222#define GPIO_BANK_C U(2)
223#define GPIO_BANK_D U(3)
224#define GPIO_BANK_E U(4)
225#define GPIO_BANK_F U(5)
226#define GPIO_BANK_G U(6)
227#define GPIO_BANK_H U(7)
228#define GPIO_BANK_I U(8)
229#define GPIO_BANK_J U(9)
230#define GPIO_BANK_K U(10)
231#define GPIO_BANK_Z U(25)
232
233#define STM32MP_GPIOZ_PIN_MAX_COUNT 8
234
235/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200236 * STM32MP1 UART
237 ******************************************************************************/
238#define USART1_BASE U(0x5C000000)
239#define USART2_BASE U(0x4000E000)
240#define USART3_BASE U(0x4000F000)
241#define UART4_BASE U(0x40010000)
242#define UART5_BASE U(0x40011000)
243#define USART6_BASE U(0x44003000)
244#define UART7_BASE U(0x40018000)
245#define UART8_BASE U(0x40019000)
Yann Gautiera2e2a302019-02-14 11:13:39 +0100246#define STM32MP_UART_BAUDRATE U(115200)
Yann Gautier038bff22019-01-17 19:17:47 +0100247
248/* For UART crash console */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100249#define STM32MP_DEBUG_USART_BASE UART4_BASE
Yann Gautier038bff22019-01-17 19:17:47 +0100250/* UART4 on HSI@64MHz, TX on GPIOG11 Alternate 6 */
Yann Gautiera2e2a302019-02-14 11:13:39 +0100251#define STM32MP_DEBUG_USART_CLK_FRQ 64000000
Yann Gautier038bff22019-01-17 19:17:47 +0100252#define DEBUG_UART_TX_GPIO_BANK_ADDRESS GPIOG_BASE
253#define DEBUG_UART_TX_GPIO_BANK_CLK_REG RCC_MP_AHB4ENSETR
254#define DEBUG_UART_TX_GPIO_BANK_CLK_EN RCC_MP_AHB4ENSETR_GPIOGEN
255#define DEBUG_UART_TX_GPIO_PORT 11
256#define DEBUG_UART_TX_GPIO_ALTERNATE 6
257#define DEBUG_UART_TX_CLKSRC_REG RCC_UART24CKSELR
258#define DEBUG_UART_TX_CLKSRC RCC_UART24CKSELR_HSI
259#define DEBUG_UART_TX_EN_REG RCC_MP_APB1ENSETR
260#define DEBUG_UART_TX_EN RCC_MP_APB1ENSETR_UART4EN
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200261
262/*******************************************************************************
Etienne Carrieree96162e2020-04-10 11:32:54 +0200263 * STM32MP1 ETZPC
264 ******************************************************************************/
265#define STM32MP1_ETZPC_BASE U(0x5C007000)
266
267/* ETZPC TZMA IDs */
268#define STM32MP1_ETZPC_TZMA_ROM U(0)
269#define STM32MP1_ETZPC_TZMA_SYSRAM U(1)
270
271#define STM32MP1_ETZPC_TZMA_ALL_SECURE GENMASK_32(9, 0)
272
273/* ETZPC DECPROT IDs */
274#define STM32MP1_ETZPC_STGENC_ID 0
275#define STM32MP1_ETZPC_BKPSRAM_ID 1
276#define STM32MP1_ETZPC_IWDG1_ID 2
277#define STM32MP1_ETZPC_USART1_ID 3
278#define STM32MP1_ETZPC_SPI6_ID 4
279#define STM32MP1_ETZPC_I2C4_ID 5
280#define STM32MP1_ETZPC_RNG1_ID 7
281#define STM32MP1_ETZPC_HASH1_ID 8
282#define STM32MP1_ETZPC_CRYP1_ID 9
283#define STM32MP1_ETZPC_DDRCTRL_ID 10
284#define STM32MP1_ETZPC_DDRPHYC_ID 11
285#define STM32MP1_ETZPC_I2C6_ID 12
286#define STM32MP1_ETZPC_SEC_ID_LIMIT 13
287
288#define STM32MP1_ETZPC_TIM2_ID 16
289#define STM32MP1_ETZPC_TIM3_ID 17
290#define STM32MP1_ETZPC_TIM4_ID 18
291#define STM32MP1_ETZPC_TIM5_ID 19
292#define STM32MP1_ETZPC_TIM6_ID 20
293#define STM32MP1_ETZPC_TIM7_ID 21
294#define STM32MP1_ETZPC_TIM12_ID 22
295#define STM32MP1_ETZPC_TIM13_ID 23
296#define STM32MP1_ETZPC_TIM14_ID 24
297#define STM32MP1_ETZPC_LPTIM1_ID 25
298#define STM32MP1_ETZPC_WWDG1_ID 26
299#define STM32MP1_ETZPC_SPI2_ID 27
300#define STM32MP1_ETZPC_SPI3_ID 28
301#define STM32MP1_ETZPC_SPDIFRX_ID 29
302#define STM32MP1_ETZPC_USART2_ID 30
303#define STM32MP1_ETZPC_USART3_ID 31
304#define STM32MP1_ETZPC_UART4_ID 32
305#define STM32MP1_ETZPC_UART5_ID 33
306#define STM32MP1_ETZPC_I2C1_ID 34
307#define STM32MP1_ETZPC_I2C2_ID 35
308#define STM32MP1_ETZPC_I2C3_ID 36
309#define STM32MP1_ETZPC_I2C5_ID 37
310#define STM32MP1_ETZPC_CEC_ID 38
311#define STM32MP1_ETZPC_DAC_ID 39
312#define STM32MP1_ETZPC_UART7_ID 40
313#define STM32MP1_ETZPC_UART8_ID 41
314#define STM32MP1_ETZPC_MDIOS_ID 44
315#define STM32MP1_ETZPC_TIM1_ID 48
316#define STM32MP1_ETZPC_TIM8_ID 49
317#define STM32MP1_ETZPC_USART6_ID 51
318#define STM32MP1_ETZPC_SPI1_ID 52
319#define STM32MP1_ETZPC_SPI4_ID 53
320#define STM32MP1_ETZPC_TIM15_ID 54
321#define STM32MP1_ETZPC_TIM16_ID 55
322#define STM32MP1_ETZPC_TIM17_ID 56
323#define STM32MP1_ETZPC_SPI5_ID 57
324#define STM32MP1_ETZPC_SAI1_ID 58
325#define STM32MP1_ETZPC_SAI2_ID 59
326#define STM32MP1_ETZPC_SAI3_ID 60
327#define STM32MP1_ETZPC_DFSDM_ID 61
328#define STM32MP1_ETZPC_TT_FDCAN_ID 62
329#define STM32MP1_ETZPC_LPTIM2_ID 64
330#define STM32MP1_ETZPC_LPTIM3_ID 65
331#define STM32MP1_ETZPC_LPTIM4_ID 66
332#define STM32MP1_ETZPC_LPTIM5_ID 67
333#define STM32MP1_ETZPC_SAI4_ID 68
334#define STM32MP1_ETZPC_VREFBUF_ID 69
335#define STM32MP1_ETZPC_DCMI_ID 70
336#define STM32MP1_ETZPC_CRC2_ID 71
337#define STM32MP1_ETZPC_ADC_ID 72
338#define STM32MP1_ETZPC_HASH2_ID 73
339#define STM32MP1_ETZPC_RNG2_ID 74
340#define STM32MP1_ETZPC_CRYP2_ID 75
341#define STM32MP1_ETZPC_SRAM1_ID 80
342#define STM32MP1_ETZPC_SRAM2_ID 81
343#define STM32MP1_ETZPC_SRAM3_ID 82
344#define STM32MP1_ETZPC_SRAM4_ID 83
345#define STM32MP1_ETZPC_RETRAM_ID 84
346#define STM32MP1_ETZPC_OTG_ID 85
347#define STM32MP1_ETZPC_SDMMC3_ID 86
348#define STM32MP1_ETZPC_DLYBSD3_ID 87
349#define STM32MP1_ETZPC_DMA1_ID 88
350#define STM32MP1_ETZPC_DMA2_ID 89
351#define STM32MP1_ETZPC_DMAMUX_ID 90
352#define STM32MP1_ETZPC_FMC_ID 91
353#define STM32MP1_ETZPC_QSPI_ID 92
354#define STM32MP1_ETZPC_DLYBQ_ID 93
355#define STM32MP1_ETZPC_ETH_ID 94
356#define STM32MP1_ETZPC_RSV_ID 95
357
358#define STM32MP_ETZPC_MAX_ID 96
359
360/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200361 * STM32MP1 TZC (TZ400)
362 ******************************************************************************/
363#define STM32MP1_TZC_BASE U(0x5C006000)
364
365#define STM32MP1_TZC_A7_ID U(0)
Yann Gautiered342322019-02-15 17:33:27 +0100366#define STM32MP1_TZC_M4_ID U(1)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200367#define STM32MP1_TZC_LCD_ID U(3)
368#define STM32MP1_TZC_GPU_ID U(4)
369#define STM32MP1_TZC_MDMA_ID U(5)
370#define STM32MP1_TZC_DMA_ID U(6)
371#define STM32MP1_TZC_USB_HOST_ID U(7)
372#define STM32MP1_TZC_USB_OTG_ID U(8)
373#define STM32MP1_TZC_SDMMC_ID U(9)
374#define STM32MP1_TZC_ETH_ID U(10)
375#define STM32MP1_TZC_DAP_ID U(15)
376
Yann Gautierf9d40d52019-01-17 14:41:46 +0100377#define STM32MP1_FILTER_BIT_ALL U(3)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200378
379/*******************************************************************************
380 * STM32MP1 SDMMC
381 ******************************************************************************/
Yann Gautiera2e2a302019-02-14 11:13:39 +0100382#define STM32MP_SDMMC1_BASE U(0x58005000)
383#define STM32MP_SDMMC2_BASE U(0x58007000)
384#define STM32MP_SDMMC3_BASE U(0x48004000)
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200385
Yann Gautier4baf5822019-05-09 13:25:52 +0200386#define STM32MP_MMC_INIT_FREQ U(400000) /*400 KHz*/
387#define STM32MP_SD_NORMAL_SPEED_MAX_FREQ U(25000000) /*25 MHz*/
388#define STM32MP_SD_HIGH_SPEED_MAX_FREQ U(50000000) /*50 MHz*/
389#define STM32MP_EMMC_NORMAL_SPEED_MAX_FREQ U(26000000) /*26 MHz*/
390#define STM32MP_EMMC_HIGH_SPEED_MAX_FREQ U(52000000) /*52 MHz*/
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200391
392/*******************************************************************************
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100393 * STM32MP1 BSEC / OTP
394 ******************************************************************************/
395#define STM32MP1_OTP_MAX_ID 0x5FU
396#define STM32MP1_UPPER_OTP_START 0x20U
397
398#define OTP_MAX_SIZE (STM32MP1_OTP_MAX_ID + 1U)
399
400/* OTP offsets */
401#define DATA0_OTP U(0)
Yann Gautierc7374052019-06-04 18:02:37 +0200402#define PART_NUMBER_OTP U(1)
Lionel Debieve402a46b2019-11-04 12:28:15 +0100403#define NAND_OTP U(9)
Yann Gautierc7374052019-06-04 18:02:37 +0200404#define PACKAGE_OTP U(16)
Yann Gautier3edc7c32019-05-20 19:17:08 +0200405#define HW2_OTP U(18)
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100406
407/* OTP mask */
408/* DATA0 */
409#define DATA0_OTP_SECURED BIT(6)
410
Yann Gautierc7374052019-06-04 18:02:37 +0200411/* PART NUMBER */
412#define PART_NUMBER_OTP_PART_MASK GENMASK_32(7, 0)
413#define PART_NUMBER_OTP_PART_SHIFT 0
414
415/* PACKAGE */
416#define PACKAGE_OTP_PKG_MASK GENMASK_32(29, 27)
417#define PACKAGE_OTP_PKG_SHIFT 27
418
Yann Gautier091eab52019-06-04 18:06:34 +0200419/* IWDG OTP */
420#define HW2_OTP_IWDG_HW_POS U(3)
421#define HW2_OTP_IWDG_FZ_STOP_POS U(5)
422#define HW2_OTP_IWDG_FZ_STANDBY_POS U(7)
423
Yann Gautier3edc7c32019-05-20 19:17:08 +0200424/* HW2 OTP */
425#define HW2_OTP_PRODUCT_BELOW_2V5 BIT(13)
426
Lionel Debieve402a46b2019-11-04 12:28:15 +0100427/* NAND OTP */
428/* NAND parameter storage flag */
429#define NAND_PARAM_STORED_IN_OTP BIT(31)
430
431/* NAND page size in bytes */
432#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
433#define NAND_PAGE_SIZE_SHIFT 29
434#define NAND_PAGE_SIZE_2K U(0)
435#define NAND_PAGE_SIZE_4K U(1)
436#define NAND_PAGE_SIZE_8K U(2)
437
438/* NAND block size in pages */
439#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
440#define NAND_BLOCK_SIZE_SHIFT 27
441#define NAND_BLOCK_SIZE_64_PAGES U(0)
442#define NAND_BLOCK_SIZE_128_PAGES U(1)
443#define NAND_BLOCK_SIZE_256_PAGES U(2)
444
445/* NAND number of block (in unit of 256 blocs) */
446#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
447#define NAND_BLOCK_NB_SHIFT 19
448#define NAND_BLOCK_NB_UNIT U(256)
449
450/* NAND bus width in bits */
451#define NAND_WIDTH_MASK BIT(18)
452#define NAND_WIDTH_SHIFT 18
453
454/* NAND number of ECC bits per 512 bytes */
455#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
456#define NAND_ECC_BIT_NB_SHIFT 15
457#define NAND_ECC_BIT_NB_UNSET U(0)
458#define NAND_ECC_BIT_NB_1_BITS U(1)
459#define NAND_ECC_BIT_NB_4_BITS U(2)
460#define NAND_ECC_BIT_NB_8_BITS U(3)
461#define NAND_ECC_ON_DIE U(4)
462
Lionel Debieve186b0462019-09-24 18:30:12 +0200463/* NAND number of planes */
464#define NAND_PLANE_BIT_NB_MASK BIT(14)
465
Yann Gautier36a1e4b2019-01-17 14:52:47 +0100466/*******************************************************************************
Yann Gautier41934662018-07-20 11:36:05 +0200467 * STM32MP1 TAMP
468 ******************************************************************************/
469#define TAMP_BASE U(0x5C00A000)
470#define TAMP_BKP_REGISTER_BASE (TAMP_BASE + U(0x100))
471
Julius Werner53456fc2019-07-09 13:49:11 -0700472#if !(defined(__LINKER__) || defined(__ASSEMBLER__))
Yann Gautier41934662018-07-20 11:36:05 +0200473static inline uint32_t tamp_bkpr(uint32_t idx)
474{
475 return TAMP_BKP_REGISTER_BASE + (idx << 2);
476}
477#endif
478
479/*******************************************************************************
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200480 * STM32MP1 DDRCTRL
481 ******************************************************************************/
482#define DDRCTRL_BASE U(0x5A003000)
483
484/*******************************************************************************
485 * STM32MP1 DDRPHYC
486 ******************************************************************************/
487#define DDRPHYC_BASE U(0x5A004000)
488
489/*******************************************************************************
Yann Gautier091eab52019-06-04 18:06:34 +0200490 * STM32MP1 IWDG
491 ******************************************************************************/
492#define IWDG_MAX_INSTANCE U(2)
493#define IWDG1_INST U(0)
494#define IWDG2_INST U(1)
495
496#define IWDG1_BASE U(0x5C003000)
497#define IWDG2_BASE U(0x5A002000)
498
499/*******************************************************************************
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200500 * Miscellaneous STM32MP1 peripherals base address
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200501 ******************************************************************************/
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200502#define CRYP1_BASE U(0x54001000)
Yann Gautier091eab52019-06-04 18:06:34 +0200503#define DBGMCU_BASE U(0x50081000)
Etienne Carriere0cfbff92020-05-13 10:16:21 +0200504#define HASH1_BASE U(0x54002000)
505#define I2C4_BASE U(0x5C002000)
506#define I2C6_BASE U(0x5c009000)
507#define RNG1_BASE U(0x54003000)
508#define RTC_BASE U(0x5c004000)
509#define SPI6_BASE U(0x5c001000)
Yann Gautier091eab52019-06-04 18:06:34 +0200510
511/*******************************************************************************
Yann Gautier4d429472019-02-14 11:15:20 +0100512 * Device Tree defines
513 ******************************************************************************/
Yann Gautier35dc0772019-05-13 18:34:48 +0200514#define DT_BSEC_COMPAT "st,stm32mp15-bsec"
Yann Gautier091eab52019-06-04 18:06:34 +0200515#define DT_IWDG_COMPAT "st,stm32mp1-iwdg"
Yann Gautier4ede20a2020-09-18 15:04:14 +0200516#define DT_PWR_COMPAT "st,stm32mp1,pwr-reg"
Yann Gautier4d429472019-02-14 11:15:20 +0100517#define DT_RCC_CLK_COMPAT "st,stm32mp1-rcc"
Yann Gautier3edc7c32019-05-20 19:17:08 +0200518#define DT_SYSCFG_COMPAT "st,stm32mp157-syscfg"
Yann Gautier4d429472019-02-14 11:15:20 +0100519
Yann Gautier4b0c72a2018-07-16 10:54:09 +0200520#endif /* STM32MP1_DEF_H */