blob: b4c9fcc1893839dda4814b1ab9a84bdf90234069 [file] [log] [blame]
Samuel Holland321c0ab2017-08-12 04:07:39 -05001/*
Samuel Hollandc629daf2019-02-17 15:33:33 -06002 * Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
Samuel Holland321c0ab2017-08-12 04:07:39 -05003 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
Andre Przywara6d0b81b2018-09-28 00:43:32 +01007#include <assert.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +00008
Samuel Holland321c0ab2017-08-12 04:07:39 -05009#include <platform_def.h>
Antonio Nino Diaze0f90632018-12-14 00:18:21 +000010
11#include <arch_helpers.h>
12#include <common/debug.h>
13#include <drivers/delay_timer.h>
14#include <lib/mmio.h>
15#include <lib/utils_def.h>
16#include <plat/common/platform.h>
17
18#include <core_off_arisc.h>
Samuel Holland321c0ab2017-08-12 04:07:39 -050019#include <sunxi_cpucfg.h>
Andre Przywara6d0b81b2018-09-28 00:43:32 +010020#include <sunxi_mmap.h>
Andre Przywara456208a2018-10-14 12:02:02 +010021#include <sunxi_private.h>
Samuel Holland321c0ab2017-08-12 04:07:39 -050022
Samuel Holland321c0ab2017-08-12 04:07:39 -050023static void sunxi_cpu_disable_power(unsigned int cluster, unsigned int core)
24{
25 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0xff)
26 return;
27
Andre Przywara8501d092018-06-22 01:33:34 +010028 VERBOSE("PSCI: Disabling power to cluster %d core %d\n", cluster, core);
Samuel Holland321c0ab2017-08-12 04:07:39 -050029
30 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xff);
31}
32
33static void sunxi_cpu_enable_power(unsigned int cluster, unsigned int core)
34{
35 if (mmio_read_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core)) == 0)
36 return;
37
Andre Przywara8501d092018-06-22 01:33:34 +010038 VERBOSE("PSCI: Enabling power to cluster %d core %d\n", cluster, core);
Samuel Holland321c0ab2017-08-12 04:07:39 -050039
40 /* Power enable sequence from original Allwinner sources */
41 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xfe);
42 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xf8);
43 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0xe0);
44 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x80);
45 mmio_write_32(SUNXI_CPU_POWER_CLAMP_REG(cluster, core), 0x00);
46}
47
Samuel Hollandc629daf2019-02-17 15:33:33 -060048void sunxi_cpu_off(u_register_t mpidr)
Samuel Holland321c0ab2017-08-12 04:07:39 -050049{
Samuel Hollandc629daf2019-02-17 15:33:33 -060050 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
51 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
Andre Przywara6d0b81b2018-09-28 00:43:32 +010052
Andre Przywara8501d092018-06-22 01:33:34 +010053 VERBOSE("PSCI: Powering off cluster %d core %d\n", cluster, core);
Samuel Holland321c0ab2017-08-12 04:07:39 -050054
55 /* Deassert DBGPWRDUP */
56 mmio_clrbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
Andre Przywara6d0b81b2018-09-28 00:43:32 +010057
58 /* We can't turn ourself off like this, but it works for other cores. */
Samuel Hollandc629daf2019-02-17 15:33:33 -060059 if (read_mpidr() != mpidr) {
Andre Przywara6d0b81b2018-09-28 00:43:32 +010060 /* Activate the core output clamps, but not for core 0. */
Samuel Hollandc629daf2019-02-17 15:33:33 -060061 if (core != 0)
Andre Przywara6d0b81b2018-09-28 00:43:32 +010062 mmio_setbits_32(SUNXI_POWEROFF_GATING_REG(cluster),
63 BIT(core));
64 /* Assert CPU power-on reset */
65 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
66 /* Remove power from the CPU */
67 sunxi_cpu_disable_power(cluster, core);
68
69 return;
70 }
71
72 /* Simplifies assembly, all SoCs so far are single cluster anyway. */
73 assert(cluster == 0);
74
75 /*
76 * If we are supposed to turn ourself off, tell the arisc SCP
77 * to do that work for us. The code expects the core mask to be
78 * patched into the first instruction.
79 */
80 sunxi_execute_arisc_code(arisc_core_off, sizeof(arisc_core_off),
81 0, BIT_32(core));
Samuel Holland321c0ab2017-08-12 04:07:39 -050082}
83
Samuel Hollandc629daf2019-02-17 15:33:33 -060084void sunxi_cpu_on(u_register_t mpidr)
Samuel Holland321c0ab2017-08-12 04:07:39 -050085{
Samuel Hollandc629daf2019-02-17 15:33:33 -060086 unsigned int cluster = MPIDR_AFFLVL1_VAL(mpidr);
87 unsigned int core = MPIDR_AFFLVL0_VAL(mpidr);
88
Andre Przywara8501d092018-06-22 01:33:34 +010089 VERBOSE("PSCI: Powering on cluster %d core %d\n", cluster, core);
Samuel Holland321c0ab2017-08-12 04:07:39 -050090
91 /* Assert CPU core reset */
92 mmio_clrbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
93 /* Assert CPU power-on reset */
94 mmio_clrbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
95 /* Set CPU to start in AArch64 mode */
96 mmio_setbits_32(SUNXI_CPUCFG_CLS_CTRL_REG0(cluster), BIT(24 + core));
97 /* Apply power to the CPU */
98 sunxi_cpu_enable_power(cluster, core);
99 /* Release the core output clamps */
100 mmio_clrbits_32(SUNXI_POWEROFF_GATING_REG(cluster), BIT(core));
101 /* Deassert CPU power-on reset */
102 mmio_setbits_32(SUNXI_POWERON_RST_REG(cluster), BIT(core));
103 /* Deassert CPU core reset */
104 mmio_setbits_32(SUNXI_CPUCFG_RST_CTRL_REG(cluster), BIT(core));
105 /* Assert DBGPWRDUP */
106 mmio_setbits_32(SUNXI_CPUCFG_DBG_REG0, BIT(core));
107}
108
Samuel Hollandc629daf2019-02-17 15:33:33 -0600109void sunxi_disable_secondary_cpus(u_register_t primary_mpidr)
Samuel Holland321c0ab2017-08-12 04:07:39 -0500110{
Samuel Hollandc629daf2019-02-17 15:33:33 -0600111 unsigned int cluster;
112 unsigned int core;
113
114 for (cluster = 0; cluster < PLATFORM_CLUSTER_COUNT; ++cluster) {
115 for (core = 0; core < PLATFORM_MAX_CPUS_PER_CLUSTER; ++core) {
116 u_register_t mpidr = (cluster << MPIDR_AFF1_SHIFT) |
117 (core << MPIDR_AFF0_SHIFT) |
118 BIT(31);
119 if (mpidr != primary_mpidr)
120 sunxi_cpu_off(mpidr);
121 }
Samuel Holland321c0ab2017-08-12 04:07:39 -0500122 }
123}