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Andrew Thoelke8c28fe02014-06-02 11:40:35 +01001/*
Soby Mathewa0fedc42016-06-16 14:52:04 +01002 * Copyright (c) 2014-2016, ARM Limited and Contributors. All rights reserved.
Andrew Thoelke8c28fe02014-06-02 11:40:35 +01003 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#ifndef __CPU_DATA_H__
32#define __CPU_DATA_H__
33
Soby Mathew748be1d2016-05-05 14:10:46 +010034#ifdef AARCH32
35
36#if CRASH_REPORTING
37#error "Crash reporting is not supported in AArch32"
38#endif
39#define CPU_DATA_CPU_OPS_PTR 0x0
40
41#else /* AARCH32 */
42
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010043/* Offsets for the cpu_data structure */
Soby Mathew523d6332015-01-08 18:02:19 +000044#define CPU_DATA_CRASH_BUF_OFFSET 0x18
Soby Mathew748be1d2016-05-05 14:10:46 +010045/* need enough space in crash buffer to save 8 registers */
46#define CPU_DATA_CRASH_BUF_SIZE 64
47#define CPU_DATA_CPU_OPS_PTR 0x10
48
49#endif /* AARCH32 */
50
Soby Mathewc1adbbc2014-06-25 10:07:40 +010051#if CRASH_REPORTING
52#define CPU_DATA_LOG2SIZE 7
dp-arm3cac7862016-09-19 11:18:44 +010053#define CPU_DATA_CRASH_BUF_END (CPU_DATA_CRASH_BUF_OFFSET + \
54 CPU_DATA_CRASH_BUF_SIZE)
Soby Mathewc1adbbc2014-06-25 10:07:40 +010055#else
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010056#define CPU_DATA_LOG2SIZE 6
dp-arm3cac7862016-09-19 11:18:44 +010057#define CPU_DATA_CRASH_BUF_END CPU_DATA_CRASH_BUF_OFFSET
Soby Mathewc1adbbc2014-06-25 10:07:40 +010058#endif
Soby Mathewc704cbc2014-08-14 11:33:56 +010059
dp-arm3cac7862016-09-19 11:18:44 +010060#if ENABLE_RUNTIME_INSTRUMENTATION
61/* Temporary space to store PMF timestamps from assembly code */
62#define CPU_DATA_PMF_TS_COUNT 1
63#define CPU_DATA_PMF_TS0_OFFSET CPU_DATA_CRASH_BUF_END
64#define CPU_DATA_PMF_TS0_IDX 0
65#endif
66
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010067#ifndef __ASSEMBLY__
68
69#include <arch_helpers.h>
Soby Mathew523d6332015-01-08 18:02:19 +000070#include <cassert.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010071#include <platform_def.h>
Achin Guptaf3ccbab2014-07-25 14:52:47 +010072#include <psci.h>
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010073#include <stdint.h>
74
Soby Mathew523d6332015-01-08 18:02:19 +000075/* Offsets for the cpu_data structure */
76#define CPU_DATA_PSCI_LOCK_OFFSET __builtin_offsetof\
77 (cpu_data_t, psci_svc_cpu_data.pcpu_bakery_info)
78
79#if PLAT_PCPU_DATA_SIZE
80#define CPU_DATA_PLAT_PCPU_OFFSET __builtin_offsetof\
81 (cpu_data_t, platform_cpu_data)
82#endif
83
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010084/*******************************************************************************
85 * Function & variable prototypes
86 ******************************************************************************/
87
88/*******************************************************************************
89 * Cache of frequently used per-cpu data:
Andrew Thoelkec02dbd62014-06-02 10:00:25 +010090 * Pointers to non-secure and secure security state contexts
Andrew Thoelke8c28fe02014-06-02 11:40:35 +010091 * Address of the crash stack
92 * It is aligned to the cache line boundary to allow efficient concurrent
93 * manipulation of these pointers on different cpus
94 *
95 * TODO: Add other commonly used variables to this (tf_issues#90)
96 *
97 * The data structure and the _cpu_data accessors should not be used directly
98 * by components that have per-cpu members. The member access macros should be
99 * used for this.
100 ******************************************************************************/
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100101typedef struct cpu_data {
Soby Mathew748be1d2016-05-05 14:10:46 +0100102#ifndef AARCH32
Andrew Thoelkec02dbd62014-06-02 10:00:25 +0100103 void *cpu_context[2];
Soby Mathew748be1d2016-05-05 14:10:46 +0100104#endif
Soby Mathewa0fedc42016-06-16 14:52:04 +0100105 uintptr_t cpu_ops_ptr;
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100106#if CRASH_REPORTING
Soby Mathewa0fedc42016-06-16 14:52:04 +0100107 u_register_t crash_buf[CPU_DATA_CRASH_BUF_SIZE >> 3];
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100108#endif
dp-arm3cac7862016-09-19 11:18:44 +0100109#if ENABLE_RUNTIME_INSTRUMENTATION
110 uint64_t cpu_data_pmf_ts[CPU_DATA_PMF_TS_COUNT];
111#endif
Soby Mathew523d6332015-01-08 18:02:19 +0000112 struct psci_cpu_data psci_svc_cpu_data;
113#if PLAT_PCPU_DATA_SIZE
114 uint8_t platform_cpu_data[PLAT_PCPU_DATA_SIZE];
115#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100116} __aligned(CACHE_WRITEBACK_GRANULE) cpu_data_t;
117
Soby Mathewc1adbbc2014-06-25 10:07:40 +0100118#if CRASH_REPORTING
119/* verify assembler offsets match data structures */
120CASSERT(CPU_DATA_CRASH_BUF_OFFSET == __builtin_offsetof
121 (cpu_data_t, crash_buf),
122 assert_cpu_data_crash_stack_offset_mismatch);
123#endif
124
125CASSERT((1 << CPU_DATA_LOG2SIZE) == sizeof(cpu_data_t),
126 assert_cpu_data_log2size_mismatch);
127
Soby Mathewc704cbc2014-08-14 11:33:56 +0100128CASSERT(CPU_DATA_CPU_OPS_PTR == __builtin_offsetof
129 (cpu_data_t, cpu_ops_ptr),
130 assert_cpu_data_cpu_ops_ptr_offset_mismatch);
131
dp-arm3cac7862016-09-19 11:18:44 +0100132#if ENABLE_RUNTIME_INSTRUMENTATION
133CASSERT(CPU_DATA_PMF_TS0_OFFSET == __builtin_offsetof
134 (cpu_data_t, cpu_data_pmf_ts[0]),
135 assert_cpu_data_pmf_ts0_offset_mismatch);
136#endif
137
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100138struct cpu_data *_cpu_data_by_index(uint32_t cpu_index);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100139
Soby Mathew748be1d2016-05-05 14:10:46 +0100140#ifndef AARCH32
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100141/* Return the cpu_data structure for the current CPU. */
142static inline struct cpu_data *_cpu_data(void)
143{
144 return (cpu_data_t *)read_tpidr_el3();
145}
Soby Mathew748be1d2016-05-05 14:10:46 +0100146#else
147struct cpu_data *_cpu_data(void);
148#endif
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100149
150/**************************************************************************
151 * APIs for initialising and accessing per-cpu data
152 *************************************************************************/
153
154void init_cpu_data_ptr(void);
Vikram Kanigiri9b38fc82015-01-29 18:27:38 +0000155void init_cpu_ops(void);
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100156
157#define get_cpu_data(_m) _cpu_data()->_m
158#define set_cpu_data(_m, _v) _cpu_data()->_m = _v
159#define get_cpu_data_by_index(_ix, _m) _cpu_data_by_index(_ix)->_m
160#define set_cpu_data_by_index(_ix, _m, _v) _cpu_data_by_index(_ix)->_m = _v
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100161
Soby Mathew24ab34f2016-05-03 17:11:42 +0100162#define flush_cpu_data(_m) flush_dcache_range((uintptr_t) \
Achin Guptae4b9fa42014-07-25 14:47:05 +0100163 &(_cpu_data()->_m), \
164 sizeof(_cpu_data()->_m))
Soby Mathew24ab34f2016-05-03 17:11:42 +0100165#define inv_cpu_data(_m) inv_dcache_range((uintptr_t) \
Soby Mathew85dbf5a2015-04-07 12:16:56 +0100166 &(_cpu_data()->_m), \
167 sizeof(_cpu_data()->_m))
Soby Mathew7d861ea2014-11-18 10:14:14 +0000168#define flush_cpu_data_by_index(_ix, _m) \
Soby Mathewa0fedc42016-06-16 14:52:04 +0100169 flush_dcache_range((uintptr_t) \
Soby Mathew7d861ea2014-11-18 10:14:14 +0000170 &(_cpu_data_by_index(_ix)->_m), \
171 sizeof(_cpu_data_by_index(_ix)->_m))
Achin Guptae4b9fa42014-07-25 14:47:05 +0100172
Andrew Thoelke8c28fe02014-06-02 11:40:35 +0100173
174#endif /* __ASSEMBLY__ */
175#endif /* __CPU_DATA_H__ */