Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 1 | /* |
Jiafei Pan | def7edc | 2021-09-10 18:54:56 +0800 | [diff] [blame] | 2 | * Copyright 2018-2021 NXP |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 3 | * |
| 4 | * SPDX-License-Identifier: BSD-3-Clause |
| 5 | * |
| 6 | */ |
| 7 | |
| 8 | #ifndef PLAT_PSCI_H |
| 9 | #define PLAT_PSCI_H |
Jiafei Pan | def7edc | 2021-09-10 18:54:56 +0800 | [diff] [blame] | 10 | #include <cortex_a53.h> |
| 11 | #include <cortex_a72.h> |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 12 | |
| 13 | /* core abort current op */ |
| 14 | #define CORE_ABORT_OP 0x1 |
| 15 | |
| 16 | /* psci power levels - these are actually affinity levels |
| 17 | * in the psci_power_state_t array |
| 18 | */ |
| 19 | #define PLAT_CORE_LVL PSCI_CPU_PWR_LVL |
| 20 | #define PLAT_CLSTR_LVL U(1) |
| 21 | #define PLAT_SYS_LVL U(2) |
| 22 | #define PLAT_MAX_LVL PLAT_SYS_LVL |
| 23 | |
| 24 | /* core state */ |
| 25 | /* OFF states 0x0 - 0xF */ |
| 26 | #define CORE_IN_RESET 0x0 |
| 27 | #define CORE_DISABLED 0x1 |
| 28 | #define CORE_OFF 0x2 |
| 29 | #define CORE_STANDBY 0x3 |
| 30 | #define CORE_PWR_DOWN 0x4 |
| 31 | #define CORE_WFE 0x6 |
| 32 | #define CORE_WFI 0x7 |
| 33 | #define CORE_LAST 0x8 |
| 34 | #define CORE_OFF_PENDING 0x9 |
| 35 | #define CORE_WORKING_INIT 0xA |
| 36 | #define SYS_OFF_PENDING 0xB |
| 37 | #define SYS_OFF 0xC |
| 38 | |
| 39 | /* ON states 0x10 - 0x1F */ |
| 40 | #define CORE_PENDING 0x10 |
| 41 | #define CORE_RELEASED 0x11 |
| 42 | #define CORE_WAKEUP 0x12 |
| 43 | /* highest off state */ |
| 44 | #define CORE_OFF_MAX 0xF |
| 45 | /* lowest on state */ |
| 46 | #define CORE_ON_MIN CORE_PENDING |
| 47 | |
| 48 | #define DAIF_SET_MASK 0x3C0 |
| 49 | #define SCTLR_I_C_M_MASK 0x00001005 |
| 50 | #define SCTLR_C_MASK 0x00000004 |
| 51 | #define SCTLR_I_MASK 0x00001000 |
| 52 | #define CPUACTLR_L1PCTL_MASK 0x0000E000 |
| 53 | #define DCSR_RCPM2_BASE 0x20170000 |
| 54 | #define CPUECTLR_SMPEN_MASK 0x40 |
| 55 | #define CPUECTLR_SMPEN_EN 0x40 |
| 56 | #define CPUECTLR_RET_MASK 0x7 |
| 57 | #define CPUECTLR_RET_SET 0x2 |
| 58 | #define CPUECTLR_TIMER_MASK 0x7 |
| 59 | #define CPUECTLR_TIMER_8TICKS 0x2 |
| 60 | #define SCR_IRQ_MASK 0x2 |
| 61 | #define SCR_FIQ_MASK 0x4 |
| 62 | |
| 63 | /* pwr mgmt features supported in the soc-specific code: |
| 64 | * value == 0x0, the soc code does not support this feature |
| 65 | * value != 0x0, the soc code supports this feature |
| 66 | */ |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 67 | #ifndef SOC_CORE_RELEASE |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 68 | #define SOC_CORE_RELEASE 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 69 | #endif |
| 70 | |
| 71 | #ifndef SOC_CORE_RESTART |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 72 | #define SOC_CORE_RESTART 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 73 | #endif |
| 74 | |
| 75 | #ifndef SOC_CORE_OFF |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 76 | #define SOC_CORE_OFF 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 77 | #endif |
| 78 | |
| 79 | #ifndef SOC_CORE_STANDBY |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 80 | #define SOC_CORE_STANDBY 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 81 | #endif |
| 82 | |
| 83 | #ifndef SOC_CORE_PWR_DWN |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 84 | #define SOC_CORE_PWR_DWN 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 85 | #endif |
| 86 | |
| 87 | #ifndef SOC_CLUSTER_STANDBY |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 88 | #define SOC_CLUSTER_STANDBY 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 89 | #endif |
| 90 | |
| 91 | #ifndef SOC_CLUSTER_PWR_DWN |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 92 | #define SOC_CLUSTER_PWR_DWN 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 93 | #endif |
| 94 | |
| 95 | #ifndef SOC_SYSTEM_STANDBY |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 96 | #define SOC_SYSTEM_STANDBY 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 97 | #endif |
| 98 | |
| 99 | #ifndef SOC_SYSTEM_PWR_DWN |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 100 | #define SOC_SYSTEM_PWR_DWN 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 101 | #endif |
| 102 | |
| 103 | #ifndef SOC_SYSTEM_OFF |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 104 | #define SOC_SYSTEM_OFF 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 105 | #endif |
| 106 | |
| 107 | #ifndef SOC_SYSTEM_RESET |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 108 | #define SOC_SYSTEM_RESET 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 109 | #endif |
| 110 | |
| 111 | #ifndef SOC_SYSTEM_RESET2 |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 112 | #define SOC_SYSTEM_RESET2 0x1 |
Jiafei Pan | 584c3f1 | 2021-09-10 19:01:15 +0800 | [diff] [blame^] | 113 | #endif |
Pankaj Gupta | a9e3ac2 | 2020-12-09 14:02:40 +0530 | [diff] [blame] | 114 | |
| 115 | #ifndef __ASSEMBLER__ |
| 116 | |
| 117 | void __dead2 _psci_system_reset(void); |
| 118 | void __dead2 _psci_system_off(void); |
| 119 | int _psci_cpu_on(u_register_t core_mask); |
| 120 | void _psci_cpu_prep_off(u_register_t core_mask); |
| 121 | void __dead2 _psci_cpu_off_wfi(u_register_t core_mask, |
| 122 | u_register_t wakeup_address); |
| 123 | void __dead2 _psci_cpu_pwrdn_wfi(u_register_t core_mask, |
| 124 | u_register_t wakeup_address); |
| 125 | void __dead2 _psci_sys_pwrdn_wfi(u_register_t core_mask, |
| 126 | u_register_t wakeup_address); |
| 127 | void _psci_wakeup(u_register_t core_mask); |
| 128 | void _psci_core_entr_stdby(u_register_t core_mask); |
| 129 | void _psci_core_prep_stdby(u_register_t core_mask); |
| 130 | void _psci_core_exit_stdby(u_register_t core_mask); |
| 131 | void _psci_core_prep_pwrdn(u_register_t core_mask); |
| 132 | void _psci_core_exit_pwrdn(u_register_t core_mask); |
| 133 | void _psci_clstr_prep_stdby(u_register_t core_mask); |
| 134 | void _psci_clstr_exit_stdby(u_register_t core_mask); |
| 135 | void _psci_clstr_prep_pwrdn(u_register_t core_mask); |
| 136 | void _psci_clstr_exit_pwrdn(u_register_t core_mask); |
| 137 | void _psci_sys_prep_stdby(u_register_t core_mask); |
| 138 | void _psci_sys_exit_stdby(u_register_t core_mask); |
| 139 | void _psci_sys_prep_pwrdn(u_register_t core_mask); |
| 140 | void _psci_sys_exit_pwrdn(u_register_t core_mask); |
| 141 | |
| 142 | #endif |
| 143 | |
| 144 | #endif /* __PLAT_PSCI_H__ */ |